Who’s Winning The FinFET Foundry Race?

By Mark LaPedus - 14 Aug, 2014 - Comments: 5

The leading-edge foundry business is challenging. For starters, foundry vendors require vast resources, gigantic fabs and lots of know-how. And yet, it’s still difficult to make money in this business. That has certainly proven to be the case in the planar transistor era, but the challenges and costs are escalating as foundry vendors begin to ramp up finFET technologies at the 16nm/14nm no... » read more

Executive Insight: Taher Madraswala

By Ed Sperling - 11 Aug, 2014 - Comments: 1

Semiconductor Engineering sat down with Taher Madraswala, president of Open-Silicon, to talk about future challenges, opportunities and changes. What follows are excerpts of that interview. SE: What worries you most? Madraswala: What worries me at the industry-level is the growing effect that business constraints are having on product innovation. We’ve done a very good job of advancing ... » read more

Improving 2.5D Components

By Ed Sperling - 07 Aug, 2014 - Comments: 1

A lot of attention is being focused on improving designs at established, well-tested nodes where processes are mature, yields are high, and costs are under control. So what does this mean to stacking die? For 2.5D architectures, plenty. For 3D, probably not much. Here’s why: The advantage of 2.5D is that it can utilize dies created at whatever node makes sense. While the initial discuss... » read more

Power Reduction Techniques

By Mary Ann White - 07 Aug, 2014 - Comments: 0

As 16nm and 14nm finFET process nodes come into production toward the end of this year, the performance (up to 30% vs. 28nm planar CMOS), power (~30%) and area (up to ~50%) benefits have been well documented. The same can be said for the 28nm FD-SOI process as it gains more traction in the marketplace touting similar performance and power improvements as those for FinFET when compared against i... » read more

Changing The Meaning Of Sign-Off

By Muhammad Zakir - 07 Aug, 2014 - Comments: 0

Chip development teams are faced with an ever-increasing number of power integrity and reliability challenges these days, especially as designs adopt FinFET technology. Even those with the most thorough sign-off checks often encounter unexpected surprises that quickly turn into tape-out hurdles, or worse yet, extensive re-design. The best way to avoid this scenario and ensure a smoother sign-of... » read more

Executive Insight: Satish Bagalkotkar

By Ed Sperling - 23 Jul, 2014 - Comments: 1

Semiconductor Engineering sat down with Satish Bagalkotkar, president and CEO of design services company Synapse Design to talk about massive shifts in the semiconductor industry and his vision of how these changes will alter the landscape, from chipmakers to design services to what gets built and how it will get used. What follows are excerpts of that interview. SE: What worries you most? ... » read more

DFM And Multipatterning

By Ed Sperling - 17 Jul, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss DFM at advanced nodes with Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics; Jongwook Kye, lithography modeling and architecture fellow at GlobalFoundries; David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics; Ya-Chieh Lai, engineering director for DFM/CLS silicon signoff and ver... » read more

All Roads Point Up…But When?

By Ed Sperling - 17 Jul, 2014 - Comments: 0

One of the clear messages at Semicon West this month was that stacked die are coming soon. The only question is how soon. This isn’t so simple to answer. It depends on a lot of factors, and for most of them there aren’t any clear answers. First of all, no one is certain what the cost equation will look like at 14/16nm, particularly once the process technology becomes more mature. Ther... » read more

Confusion Does Not Equal Paralysis

By Ed Sperling - 10 Jul, 2014 - Comments: 0

After attending the two biggest semiconductor conferences in the world, along with a long list of notable conferences targeted to a wide variety of technologies and engineering disciplines, it’s clear the industry is racing ahead. But “ahead” is now a relative term. While Moore’s Law satisfied both economic and technological requirements, it was easy to figure out what “ahead” me... » read more

Supporting LP In New Process Nodes

By Ann Mutschler - 10 Jul, 2014 - Comments: 0

Manufacturing process nodes and EDA tools are advancing all the time, but not always utilized at the same pace. And from a tools perspective, there are challenges to supporting low power in new process nodes while maintaining and improving the existing process nodes. One way design teams address this is by leveraging the most advanced software on the less-than-bleeding edge designs. To th... » read more

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