FinFET Based Designs: Reliability Verification Implications


Over the past few months, I’ve discussed various challenges associated with finFET-based designs. We all know that finFET devices enable design teams to operate their chips at significantly lower supply voltages with a very tight control on leakage current. But to control the overall power within a tight power budget, the challenge shifts to how the logic design is managed such that the overa... » read more

Stacked Die Are Coming Soon. Really


Since the beginning of the decade there have been many predictions that stacked die were just over the hill, but the time it has taken to climb that hill has been longer than most people would have anticipated. In fact, TSMC has been fully capable of building stacked die since last year, with risk production expected to be completed by year, according to Gartner. But something very fundament... » read more

28nm FinFETs?


One star of the upcoming 14/16nm process node is the introduction of the finFET, a fundamentally new transistor that overcomes many of the limitations associated with planar transistors. While these devices are more complex to construct—and the physical extraction processes associated with them is more complex due to an increased number of resistances and capacitances—they are seen as a tra... » read more

All Together Now!


Consolidation is changing the face of our industry. It is tempting to think that a narrower more consolidated industry is easier to navigate and might require less facilitated coordination and collaboration. However, it turns out the reverse is true. With fewer, but much bigger companies, the bets become exponentially bigger.  At the same time technical challenges — such as advanced tra... » read more

Semiconductor R&D Crisis Ahead?


Listen to engineering management at chipmakers these days and a consistent theme emerges: They’re all petrified about where to place their next technology bets. Do they move to 14/16nm finFETs with plans to shrink to 10nm, 7nm and maybe even 5nm? Do they invest in 2.5D and 3D stacked die? Or do they eke more from existing process nodes using new process technologies, more compact designs and ... » read more

Without Moore’s Law: EDA


Semiconductor Engineering is examining the assertion about the end of Moore’s Law in a number of different ways. The special report, “Will 7nm and 5nm really happen?” looked at the technical aspects related to continuing into finer geometries. “Moore’s Law Tail No Longer Wagging the Dog” asked the question about the economics of people being able to afford to go to the latest node. ... » read more

The Week In Review: Design


Tools Mentor Graphics uncorked a tool for IC, package and board optimization, assembly and visualization. Of particular note is a “virtual die model” capability, which can be used across multiple domains in the design process. Deals Rambus inked a patent licensing agreement with Qualcomm Global Trading, a subsidiary of Qualcomm, for memory, interface and security technologies. The secu... » read more

Blog Review: June 11


eSilicon’s Jack Harding says that EDA and semiconductors need to focus heavily on recruiting the next generation of brilliant engineers. This technology is cool, and even better it makes all the other cool technology work. It’s time to remind the rest of the world. Cadence’s Brian Fuller distills a panel discussion at DAC on computer vision—the sensors that enable driverless cars, a... » read more

DAC Day One


The Design Automation Confeence got off to a roaring start today and the Synopsys breakfast and keynote were standing room only. The Synopsys breakfast brought together foundry (Samsung), IP developer (Arm) and tool provider (Synopsys) to talk about the growing requirements of ecosystems and partnership in order to make new processes available for production usage. Perhaps the most surprisin... » read more

EDA Races To 7nm, Despite Litho Uncertainties


It’s becoming almost painful to refer to the delay with EUV, but it certainly isn’t stopping anyone on the design side from tweaking design tools or working on test chips. Clearly, things are moving ahead to 7nm even though lithography plans aren't yet clear. Steve Carlson, group marketing director in Cadence’s Office of Chief Strategy, said with regard to EUV, “They have the power p... » read more

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