tag: 16nm

More Than Moore
By Ed Sperling - 15 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

How Reliable Is Your IP?
By Ed Sperling - 12 Sep, 2014 - Comments: 0

Almost everyone who has bought a new smartphone, car, home electronics device or appliance either has experienced technical glitches that require a replacement or repair, or they know someone who has experienced these problems. The good news is that only a very small fraction of the electronic glitches or failures can be contributed to hardware design. Most of it is due to manufacturing vari... » read more

Making Chips Run Faster
By Ed Sperling - 11 Sep, 2014 - Comments: 3

For all the talk about low power, the real focus of most chipmakers is still performance. The reality is that OEMs might be willing to sacrifice increasing performance for longer battery life, but they will rarely lower performance to reach that goal. This is more obvious for some applications than others. A machine monitor probably isn’t the place where performance will make much of a dif... » read more

More Problems Ahead
By Ed Sperling - 10 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss future scaling problems with Lars Liebmann, a fellow at IBM; Adam Brand, managing director of transistor technology at Applied Materials; Karim Arabi, vice president of engineering at Qualcomm; and Srinivas Banna, a fellow for advanced technology architecture at GlobalFoundries. SE: Where are the most severe issues these days? Is it on the design... » read more

More Problems Ahead
By Ed Sperling - 25 Aug, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss future scaling problems with Lars Liebmann, a fellow at IBM; Adam Brand, managing director of transistor technology at Applied Materials; Karim Arabi, vice president of engineering at Qualcomm; and Srinivas Banna, a fellow for advanced technology architecture at GlobalFoundries. SE: There seems to be some debate in this group about whether we’r... » read more

Ready To Pounce
By Ed Sperling - 21 Aug, 2014 - Comments: 0

A series of inflection points at 16/14nm and beyond is having a rather unusual effect on the semiconductor industry. Rather than forge ahead with the next nodes to gain an edge and early lead over rivals—the standard formula for success over the past five decades—the entire supply chain is poised on the edge, waiting for someone to make the first move before they take action. The problem... » read more

The Changing IP Ecosystem
By Ann Mutschler - 21 Aug, 2014 - Comments: 0

Is a larger [getkc id="43" kc_name="IP"] company better suited to deliver what users need – from hardware to software to PDKs and reference designs – with larger and more diverse teams to draw upon, as well as deep foundry relationships? Or does it pay to small, quick and nimble? The answer to that question appears to be playing out in real time. As design complexity has increased, so ha... » read more

More Than Moore
By Ed Sperling - 21 Aug, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at Open-Silicon; Patrick Soheili, vice president and general manager of IP Solutions at eSilicon; Brandon Wang, engineering group director at Cadence; John Ferguson, product manager for DRC applications at Mentor Graphics; and Kevin Kranen, d... » read more

Executive Insight: Jack Harding
By Ed Sperling - 18 Aug, 2014 - Comments: 0

SE: What’s worrying you these days? Harding: One thing that bothers me is the cost of chip development on a per-chip basis. We seduce ourselves into thinking everything is wonderful because the cost per transistor is dropping in chunks. Gate costs are going down at every node. If you look at the secular trend, we’ve done a pretty good job putting a lot of stuff in a small space. In my bu... » read more

Signoff Intensity On The Rise
By The SE Staff - 15 Aug, 2014 - Comments: 2

By Ann Steffora Mutschler and Ed Sperling Lithography and signoff are crossing swords at 16/14nm and 10nm, creating new problems that raise questions about just how confident design teams will be when they sign off before tapeout — and how many respins are likely to follow. While designs at 20nm, 16nm and 14nm typically rely on colorless double patterning, at 10nm colors are mandatory. ... » read more

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