Controlling IC Manufacturing Processes For Yield

By Ed Sperling - 24 Apr, 2019 - Comments: 0

Equipment and tools vendors are starting to focus on data as a means of improving yield, adding more sensors and analysis capabilities into the manufacturing flow to circumvent problems in real time. How much this will impact the cost of developing complex chips at leading-edge nodes, and in 2.5D and 3D-IC packages, remains to be seen. But the race to both generate data during manufacturing ... » read more

GDDR6 – HBM2 Tradeoffs

By Ed Sperling - 10 Apr, 2019 - Comments: 0

Steven Woo, Rambus fellow and distinguished inventor, talks about why designers choose one memory type over another. Applications for each were clearly delineated in the past, but the lines are starting to blur. Nevertheless, tradeoffs remain around complexity, cost, performance, and power efficiency. Related Video Latency Under Load: HBM2 vs. GDDR6 Why data traffic and bandw... » read more

Making Chip Packaging Simpler

By Ed Sperling and Mark LaPedus - 21 Mar, 2019 - Comments: 1

Packaging is emerging as one of the most critical elements in semiconductor design, but it's also proving difficult to master both technically and economically. The original role of packaging was simply to protect the chips inside, and there are still packages that do just that. But at advanced nodes, and with the integration of heterogeneous components built using different manufacturing pr... » read more

Power Budgets At 3nm And Beyond

By Ed Sperling - 14 Mar, 2019 - Comments: 0

There is high confidence that digital logic will continue to shrink at least to 3nm, and possibly down to 1.5nm. Each of those will require significant changes in how design teams approach power. This is somewhat evolutionary for most chipmakers. Five years ago there were fewer than a handful of power experts in most large organizations. Today, everyone deals with power in one way or another... » read more

2.5D, 3D Power Integrity

By Ed Sperling - 14 Mar, 2019 - Comments: 0

Chris Ortiz, principal applications engineer at ANSYS, zeroes in on some common issues that are showing up in 2.5D and 3D packaging, which were not obvious in the initial implementations of these packaging technologies. This includes everything from how to build a power delivery network to minimize the coupling between chips to dealing with variability and power integrity and placement of diffe... » read more

In-Memory Vs. Near-Memory Computing

By Mark LaPedus - 21 Feb, 2019 - Comments: 1

New memory-centric chip technologies are emerging that promise to solve the bandwidth bottleneck issues in today’s systems. The idea behind these technologies is to bring the memory closer to the processing tasks to speed up the system. This concept isn’t new and the previous versions of the technology fell short. Moreover, it’s unclear if the new approaches will live up to their billi... » read more

More 2.5D/3D, Fan-Out Packages Ahead

By Mark LaPedus - 15 Jan, 2019 - Comments: 0

A new wave of 2.5D/3D, fan-out and other advanced IC packages is expected to flood the market over the next year. The new packages are targeted to address many of the same and challenging applications in the market, such as multi-die integration, memory bandwidth issues and even chip scaling. But the new, advanced IC packages face some technical challenges. And cost remains an issue as advan... » read more

Reducing Advanced Packaging Costs

By Ed Sperling - 09 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down with Chenglin Liu, director of package engineering at Marvell; John Hunt, senior director of engineering at ASE; Eric Tosaya, senior director of package manufacturing at eSilicon; and Juan Rey, vice president of engineering for Calibre at Mentor, a Siemens Business. What follows are excerpts of that discussion, which was held in front of a live audience at MEP... » read more

Making Sense Of DRAM

By Ed Sperling - 13 Dec, 2018 - Comments: 0

Graham Allan, senior manager for product marketing at Synopsys, examines the different types of DRAM, from GDDR to HBM, which markets they’re used in, and why there is such disparity between them. https://youtu.be/ynvcPfD2cZU __________________________________ See more tech talk videos here. » read more

Where Advanced Packaging Makes Sense

By Ed Sperling - 10 Dec, 2018 - Comments: 0

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

Defining The Chiplet Socket

The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?

by Brian Bailey

tag: 2.5D

Controlling IC Manufacturing Processes For Yield

GDDR6 – HBM2 Tradeoffs

Making Chip Packaging Simpler

Power Budgets At 3nm And Beyond

2.5D, 3D Power Integrity

In-Memory Vs. Near-Memory Computing

More 2.5D/3D, Fan-Out Packages Ahead

Reducing Advanced Packaging Costs

Making Sense Of DRAM

Where Advanced Packaging Makes Sense

Trending Articles

NAND Flash Targets 1,000 Layers

Testing For Thermal Issues Becomes More Difficult

Auto Chip Aging Accelerates In Hot Climates

Is In-Memory Compute Still Alive?

Baby Steps Toward 3D DRAM

Knowledge Centers
Entities, people and technologies explored