tag: 2.5D

The Week In Review: Manufacturing
By Mark LaPedus - 17 Jul, 2015 - Comments: 0

Semicon West is always a busy week. Typically, there are a plethora of events going on during the week. It’s also a good week to get a pulse on the industry. The good news: Innovation is alive and well. Bad news: Intel cut its CapEx. And tool makers are in the midst of a lull right now, with a cloudy outlook projected for 2016. Some even see a dreaded downturn next year. Pacific Crest Secu... » read more

Here Comes 7nm
By Ed Sperling - 09 Jul, 2015 - Comments: 0

A consortium of companies involving IBM, GlobalFoundries and Samsung has rolled out the first 7nm test chip using silicon germanium as a substrate, using EUV to pattern multiple layers. While this doesn't mean the cost equation is even close to being solved, or that more than a handful of companies will push forward to that node anytime soon using SiGe as the substrate material, it does cre... » read more

IP Market Shifts Direction
By Ed Sperling - 03 Jun, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss intellectual property changes and challenges with Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and MSIP at [getentity id="22035" e_name="Synopsys"]; Kurt Shuler, vice president of marketing at [getentity i... » read more

One-On-One: Thomas Caulfield
By Mark LaPedus - 21 May, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about fabs, process technology and the equipment industry with Thomas Caulfield, senior vice president and general manager of Fab 8 at [getentity id="22819" comment="GlobalFoundries"]. Located in Saratoga County, N.Y., Fab 8 is GlobalFoundries’ most advanced 300mm wafer fab. What follows are excerpts of that discussion. SE: Last year, GlobalFoundr... » read more

Rethinking Power
By Ed Sperling - 14 May, 2015 - Comments: 0

Power typically has been the last factor to be considered in the PPA equation, and it usually was somebody else's problem. Increasingly it's everyone's problem, and EDA companies are beginning to look at power differently than in the past. While the driving forces vary by market and by process node, the need to save energy at every node and in almost all designs is pervasive. In the server m... » read more

How Switching Activity Impacts A Design’s Power And Reliability
By Chris Ortiz - 14 May, 2015 - Comments: 0

Electronics continue to gain presence in both familiar and unfamiliar areas of our lives. Electronics is a common thread among the cars we drive, the computers we use, the mobile phones and wearable devices that we rely on. We appreciate the information and convenience that Fitbits and other products such as coffee makers, credit cards and building security cards provide us. And we are beginni... » read more

FD-SOI Vs. FinFETs
By Ed Sperling - 30 Apr, 2015 - Comments: 0

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

Analysis: Applied-TEL Scrap Merger
By Mark LaPedus - 27 Apr, 2015 - Comments: 0

After several delays due to a myriad of complex regulatory issues, Applied Materials’ proposed deal to buy Tokyo Electron Ltd. (TEL) has been scrapped. It appears that the U.S. Department of Justice (DoJ) stepped in and blocked the deal. Now that the deal has been terminated, Applied Materials and TEL are separately re-grouping, and are back to where they originally started as fierce compe... » read more

Pressure Builds To Revamp The Design Flow
By Ed Sperling - 23 Apr, 2015 - Comments: 1

Without [getkc id="7" kc_name="EDA"] there would be no [getkc id="74" comment="Moore's Law"] as we know it today, and without Moore's Law there would be a much more limited need for EDA. But after more than three decades of developing design flows packed with sophisticated tools to automate semiconductor design through verification, and thereby enable feature shrinks that are the basis of Moore... » read more

Brite Semiconductor: Design Services
By Ed Sperling - 20 Apr, 2015 - Comments: 0

These days it's increasingly common for large commercial foundries to have a design services counterpart—TSMC has GlobalUnichip. GlobalFoundries has an entire ecosystem as well as a dedicated partner, Invecas. And China's SMIC has Brite Semiconductor. Brite was founded in 2008 by Open-Silicon as a way to tap the Chinese market, but the startup has taken some twists since then. It now is un... » read more

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