tag: 20nm

The Rise Of Layout-Dependent Effects
By Ann Mutschler - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Designing for today’s advanced semiconductor manufacturing process nodes brings area, speed, power and other benefits but also new performance challenges as a result of the pure physics of running current through tiny wires. Layout-dependent effects (LDE), which emerged at 40nm and are having a larger impact at 28 and 20nm, introduce variability to circuit ... » read more

Designing with FinFETs: The Opportunities and the Challenges
By Various Writers - 28 Feb, 2013 - Comments: 0

With the help of double-patterning and other advanced lithography techniques, CMOS technology continues to scale to 20-nanometer (nm) and beyond. Yet, because of their superior attributes, FinFETs are replacing planar CMOS technology as the device technology of choice at these advanced nodes. In particular, FinFETs demonstrate better results in the areas of performance, leakage and dynamic powe... » read more

Good Pattern Flow Ahead For 14, 10nm
By Ann Mutschler - 21 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node. “They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant... » read more

A New World For Fill At N20
By Mentor Graphics Staff Writers - 21 Feb, 2013 - Comments: 1

By Jeff Wilson and Jean-Marie Brunet There are many drastic changes required to design, verify, and manufacture semiconductors at the 20nm process node (N20). One of these is fill. At previous design nodes, fill was used just to ensure manufacturability by giving each layer (metal, poly, diffusion) an accepted density. At N20, fill is used to address many more manufacturing issues, and has bec... » read more

A Call To Action: How 20nm Will Change IC Design
By Various Writers - 21 Feb, 2013 - Comments: 0

The 20nm process node represents a turning point for the electronics industry. While it brings tremendous power, performance and area advantages, it also comes with new challenges in such areas as lithography, variability, and complexity. The good news is that these become manageable challenges with 20nm-aware EDA tools when they are used within end-to-end, integrated design flows based on a �... » read more

FinFETs, EUV And Moore’s Law
By Ed Sperling - 21 Feb, 2013 - Comments: 0

GlobalFoundries VP Subramani Kengeri talks about progress and problems with advanced processes with Semiconductor Manufacturing & Design. [youtube vid=_Ang0I1vWdI] » read more

28nm Powers TSMC Forward
By Barry Pangrle - 14 Feb, 2013 - Comments: 1

By Barry Pangrle TSMC’s financial results for Q4 of 2012 and for the full year were announced just a few weeks agom with TSMC stating it had achieved record sales and profits. Basically, TSMC currently owns the 28nm foundry market. Chairman Morris Chang was clear to distinguish 28nm from 32nm. TSMC substantially moved to the 40nm “half-node” from 45nm, and then skipped 32nm and went to 2... » read more

Tradeoffs On The Fly
By Ed Sperling - 17 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler With classical bulk planar technology no longer shrinkable, the industry has been honing in on new ways to continue some scaling, achieve extra speed or better power while minimizing leakage. “To overcome the limits [of bulk planar technology] we need a different solution,” explained Giorgio Cesano, technology R&D marketing director at STMicroelectron... » read more

Double Patterning From Design Enablement To Verification
By Various Writers - 13 Dec, 2012 - Comments: 0

Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal layers. We discuss the unique design and process characteristics of LELE DP, the challenges they present, and various solutions, including: DP design methodologies, current DP conflict feedback mechanisms, and how they can help designers identify and resolve conflicts. E... » read more

Increasing Levels Of Risk
By Ed Sperling - 13 Dec, 2012 - Comments: 0

Semiconductor Manufacturing & Design sits down with Mentor Graphics' Jean-Marie Brunet to talk about double patterning, finFETs, design rules at advanced nodes and why design for manufacturing (DFM) has suddenly become so popular. [youtube vid=3GHvikyjZow] » read more

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