tag: 3D-IC

Ready For 3D-IC
By Various Writers - 28 Feb, 2013 - Comments: 0

This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon interposers. To download this white paper, click here. » read more

Sprint To The Finish Line
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss future challenges, pain points, and how the supply chain is being reconfigured with Chi-Ping Hsu, senior vice president for R&D in the Silicon Realization Group at Cadence. What follows are excerpts of that conversation. LPHP: Has the move to 20nm processes with 14nm finFETs progressed as smoothly as everyone hop... » read more

Inside The Package
By Mark LaPedus - 24 Jan, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss IC packaging trends with Rich Rice, senior vice president for North America at Taiwan’s Advanced Semiconductor Engineering (ASE), the world’s largest independent IC packaging and test house. SMD: Amazingly, there are still more than 100 vendors competing in the IC test and assembly business today. But for year... » read more

Stacked Die From A Networking Angle
By Mark LaPedus - 24 Jan, 2013 - Comments: 1

By Mark LaPedus The first wave of 2.5D chips using silicon interposers are trickling out in the marketplace.FPGA vendor Xilinx was the first chipmaker to ship a 2.5D device, and Altera, Cisco, Huawei and IBM recently have talked about their respective 2.5D chip developments. Generally, Altera and Xilinx have taken a somewhat identical and straightforward approach. The two companies are sepa... » read more

Fixing The Supply Chain
By Ed Sperling - 24 Jan, 2013 - Comments: 0

For all the promise and subsequent anxiety about moving to the next process node or stacking die, the real problem isn’t technology. It isn’t even cost per transistor. It’s who will take responsibility when something goes wrong. Notice the word “when” rather than “if.” Rising complexity means that chips no longer can be fully verified, so errors are a given. Some errors are wor... » read more

3 Ways To Differentiate
By Ed Sperling - 13 Jan, 2013 - Comments: 0

Time-to-market pressures and complexity have put the squeeze on design teams. They have to bring incredibly complex SoCs to market on time, make sure they’re functionally correct and work within a tight power budget, and they have to come in on or under budget. Amazingly, they’re still able to accomplish this, thanks to some heroic efforts on the part of engineers and some incredible adv... » read more

Experts At The Table: SoC Verification
By Ed Sperling - 19 Dec, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss the challenges of verification with Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadence; Charles Janac, chairman and CEO of Arteris, Venkat Iyer, CTO of Uniquify; and Adnan Hamid, CEO of Breker Verification Systems. What follows are excerpts of that discussion. SLD: Is the amount of time... » read more

Keeping Pace With Moore’s Law
By Ann Mutschler - 19 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler As the number of transistors doubles with each move to a smaller manufacturing process technology, there are questions as to whether the current cadre of place and route tools will be able to keep in lock step. Have no fear, assured Saleem Haider, senior director of marketing for physical design and DFM at Synopsys. “For the increase in densities that we get with... » read more

Predictions, Problems And Prognosis
By Ed Sperling - 19 Dec, 2012 - Comments: 0

Never before in the long and often turbulent history of the semiconductor industry have so many problems presented themselves at each new process node. And never before have there been so many well-tested choices to resolving them. After possibly the most intensive, extensive and expensive research this industry has ever witnessed, Moore’s Law is now technologically assured down to at leas... » read more

Straight Talk On 3D TSVs
By Ed Sperling - 13 Dec, 2012 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss 3D device challenges and applications with John Lau, a fellow at the Industrial Technology Research Institute (ITRI), a research organization in Taiwan. SMD: What is ITRI doing in 3D TSVs? Lau: At ITRI we have developed the world’s first Applied Materials’ 300mm (3D TSV) integration line. The line was comple... » read more

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