tag: 3D-IC

Partition Lines Growing Fuzzy
By Ed Sperling - 26 Feb, 2015 - Comments: 0

For as long as most semiconductor engineers can remember, chips with discrete functions started out on a printed circuit board, progressed into chip sets when it made sense and eventually were integrated onto the same die. The primary motivations behind this trend were performance and cost—shorter distance, fewer mask layers, less silicon. But this equation has been changing over the past ... » read more

One-On-One: Dave Hemker
By Mark LaPedus - 19 Feb, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Dave Hemker, senior vice president and chief technology officer at [getentity id="22820" comment="LAM Research"]. SE: On the technology front, the IC industry is undergoing some new and dramatic changes. What are some of those changes? Hemker: We focus on what we call the inflections.... » read more

Back To The Future
By Ed Sperling - 02 Feb, 2015 - Comments: 0

The push to the next process node typically has meant that designs get simpler at existing and older nodes because the process technology is more mature and there have been so many chips developed at those nodes—many billions of them—that every possible corner case has been encountered hundreds, if not thousands, of times. That all makes sense in theory, but several key things have chang... » read more

Manufacturing And Packaging Changes For 2015
By Brian Bailey - 22 Jan, 2015 - Comments: 0

This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

One-On-One: Aaron Thean
By Mark LaPedus - 22 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec. SE: Chipmakers are ramping up the 16nm/14nm logic node, with 10nm and 7nm in R&D. What’s the current timeline for 10nm and 7nm? Thean: 10nm is on its way. We will see r... » read more

Designing For Security
By Ernest Worthman - 08 Jan, 2015 - Comments: 0

Stacked die may improve performance and lower power, but the use of [getkc id="203" kc_name="through-silicon vias"] (TSVs) could add new security risks. As IC structures go, the vertical component of these chip packages is both a boon and a bust. Three-dimensional geometries allow for much less complexity in design by stacking two-dimensional dies and interconnecting them in the third dimens... » read more

Is The Stacked Die Ecosystem Stagnating?
By Ann Mutschler - 23 Dec, 2014 - Comments: 0

While the stacked die ecosystem in general is currently status quo, with not much happening in the past year, there is definitely work being done —albeit cautiously—on the design tools side of things. It would be easy to feel impatient that the design tools are not complete and available today for [getkc id="82" comment="2.5D"] and [getkc id="42" comment="3D IC"] implementation until hearin... » read more

Industry Scorecard For 2014
By Brian Bailey - 18 Dec, 2014 - Comments: 0

At the end of last year, Semiconductor Engineering asked the industry about the developments they expected to see in 2014. If you care to refresh your memory, they were categorized under markets, semiconductors and development tools. Now it is time to look back and see how accurate those predictions were and where they fell short. Markets The obvious trend, at the beginning of the year, wa... » read more

Is The Stacked Die Ecosystem Stagnating?
By Ann Mutschler - 18 Dec, 2014 - Comments: 2

It is now widely agreed that not much has been happening in terms of adoption for 2.5D interposer and 3D ICs. “It seems like everyone is still at the starting line waiting for the race to begin," said Javier DeLaCruz, senior director of engineering of [getentity id="22242" e_name="eSilicon"]. "Interposer assembly and IP availability for effectively using the [getkc id="82" comment="2.5D IC... » read more

System Bits: Dec. 16
By Ann Mutschler - 16 Dec, 2014 - Comments: 0

High rise chip For decades, the mantra of the semiconductor industry has been ‘smaller, faster, cheaper.’ Stanford researchers are also adding ‘taller’ to the mix, and describing how to build high-rise chips that promise to leapfrog the performance of the single-story logic and memory chips on today's circuit cards. Stanford researchers said their approach would end the ‘logjams�... » read more

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