tag: 3D-IC

Seven Ways To Improve PPA Before Moving To FinFETs
By Ed Sperling - 05 Dec, 2013 - Comments: 0

Henry Ford wrote in his autobiography, “Any customer can have a car painted any color that he wants so long as it is black.” And for decades, the semiconductor industry has marched to a similar theme set by Moore’s Law. But with the transition to finFETs harder than it first appeared, questions are beginning to pop up that is fueling a new level of confusion. While the growing list of... » read more

Stacked Die Moves From Drawing Board To Reality
By Ed Sperling - 21 Nov, 2013 - Comments: 0

After decades of moving in a straight line from one process geometry shrink to the next, much of the semiconductor industry has taken a step back to figure out what comes next. While companies such as Intel, IBM and Samsung continue to look as far ahead as the 3nm process node, along with new materials to improve electron mobility and new transistor designs based on electron tunneling and carbo... » read more

Counting Pennies
By Ed Sperling - 21 Nov, 2013 - Comments: 0

Even Intel may not have enough cash on hand to pay for a new state-of-the-art fab at 7nm. With fully equipped fabs expected to rise into the plus-$10 billion range over the next few process nodes, and each new process shrink jam-packed with a multitude of new problems, the momentum for continuing to shrink features appears to be slowing down. Technically, it’s possible to shrink transistor... » read more

3D-IC Standardization Progress Continues
By James Amano - 14 Nov, 2013 - Comments: 1

Since its formation in December 2010, the SEMI 3DS-IC Standards Committee has made significant progress in establishing key standards in areas such as TSV metrology, glass carrier wafers, and terminology. The committee’s two newest standards are SEMI 3D6-0913 - Guide for Chemical Mechanical Planarization (CMP) and Micro-Bump Processes for Frontside Through Silicon Via (TSV) Integration, and S... » read more

From DFM To IFM
By Ed Sperling - 14 Nov, 2013 - Comments: 0

For the past decade the bridge between design and manufacturing was called, appropriately enough, design for manufacturing. DFM tools, which by nature cross boundaries of what previously were discrete segments in the semiconductor flow, are now critical for complex designs. They allow design teams to check early in the design process whether chips will yield sufficiently and to incorporate rule... » read more

Momentum Builds For Monolithic 3D ICs
By Mark LaPedus - 14 Nov, 2013 - Comments: 1

The 2.5D/3D chip market is heating up on several fronts. On one front, stacked-die using through-silicon vias (TSVs) is taking root. In a separate area, Samsung is sampling the world’s first 3D NAND device, with Micron and SK Hynix expected to follow suit. And now, there is another technology generating steam—monolithic 3D integrated circuits. In stacked-die, bare die are connected using... » read more

Temporary Bonding, Debonding Remains Challenging For TSV Adoption
By Jeff Chappell - 28 Oct, 2013 - Comments: 0

By Jeff Chappell One issue with the adoption of TSVs in 3D ICs in mainstream semiconductor applications revolves around the throughput of the temporary wafer bonding and debonding process. This doesn't necessarily equate to a roadblock, but work certainly remains to be done on this and related issues. On one hand, TSVs already are being used in the manufacturing of compound semiconductors ... » read more

TSVs: Welcome To The Era Of Probably Good Die
By Jeff Chappell - 21 Oct, 2013 - Comments: 0

Among the challenges of a widespread adoption of 3D ICs is how to test them, particularly when it comes to through-silicon vias (TSVs). While not necessarily presenting a roadblock, TSVs use in the mainstream will almost certainly change traditional test strategies. In fact for many chipmakers looking to stack their silicon, they may come to rely less on the traditional known good die (KGD) ... » read more

Standards Watch
By Ed Sperling - 17 Oct, 2013 - Comments: 0

This may sound odd to anyone outside of the SoC world, but as more functionality and more components move from PCB to chip—or at least the same package—what’s happening in the standards world is mirroring what’s going on in semiconductor design and manufacturing. The rule of thumb in the standards world is that as new techniques and technologies are introduced, the number of standard... » read more

Manufacturing Bits: Oct. 1
By Mark LaPedus - 01 Oct, 2013 - Comments: 0

Nanoimprint Foundry Singapore’s A*STAR’s Institute of Materials Research and Engineering (IMRE) and its partners have launched a new R&D foundry using nanoimprint lithography. The so-called Nanoimprint Foundry is a collaboration between several entities, such as IMRE, Toshiba Machines, EV Group, NTT, NIL Technology, Kyodo International, Micro Resist Technology, Nanoveu and Solves In... » read more

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