tag: 3D-IC

The End Is Near
By Ed Sperling - 30 Dec, 2013 - Comments: 0

Looking back is easier than looking forward, and looking narrow is easier than looking wide. In 2013, there were several fundamental changes. Change No. 1: IP is now a lucrative market. From Synopsys’ standpoint, it’s been a lucrative market for some time. But the acquisitions made by Cadence, beginning in late 2012, coupled with the push by ARM into the micro-server market and the flail... » read more

Modern IC Packaging
By Various Writers - 18 Dec, 2013 - Comments: 0

Modern IC packaging technologies, such as 3D-IC, drive the need for IC, package and system co-design tools and methodologies. To download this white paper, click here.  » read more

Different Economies Of Scale, And Lots Of Questions
By Ed Sperling - 12 Dec, 2013 - Comments: 0

Being able to shrink features and reach the next node is already an exclusive club. It will become more exclusive at 16/14nm, which is expected to hit volume production in 2015, and even more exclusive still at 10nm. In fact, it may begin to look like a semi-private affair. The argument being presented is that economies of scale will still exist for those companies with pockets deep enough ... » read more

3D-IC Requires Expanded Power Grid Analysis
By Christen Decoin - 05 Dec, 2013 - Comments: 0

At advanced nodes, effective power grid analysis is critical to ensure that the small dimension interconnects can handle current demands without introducing potential failure modes or signal integrity issues. Existing software tools for power analysis need to be extended and enhanced for 2.5D and 3D designs to fulfill new requirements and use models. This article describes some of the needed im... » read more

Thermally Challenged
By Brian Bailey - 05 Dec, 2013 - Comments: 0

Chips run hot and the thermal densities increase with every reduction in fabrication geometry. “When we go down to 16nm the local power density increases by 25% and the local gate density also increases by 25% to 30%,” explains Norman Chang, vice president of product strategy at Ansys/Apache. In fact, this is becoming such a large problem that it is affecting the scaling process itsel... » read more

Seven Ways To Improve PPA Before Moving To FinFETs
By Ed Sperling - 05 Dec, 2013 - Comments: 0

Henry Ford wrote in his autobiography, “Any customer can have a car painted any color that he wants so long as it is black.” And for decades, the semiconductor industry has marched to a similar theme set by Moore’s Law. But with the transition to finFETs harder than it first appeared, questions are beginning to pop up that is fueling a new level of confusion. While the growing list of... » read more

Stacked Die Moves From Drawing Board To Reality
By Ed Sperling - 21 Nov, 2013 - Comments: 0

After decades of moving in a straight line from one process geometry shrink to the next, much of the semiconductor industry has taken a step back to figure out what comes next. While companies such as Intel, IBM and Samsung continue to look as far ahead as the 3nm process node, along with new materials to improve electron mobility and new transistor designs based on electron tunneling and carbo... » read more

Counting Pennies
By Ed Sperling - 21 Nov, 2013 - Comments: 0

Even Intel may not have enough cash on hand to pay for a new state-of-the-art fab at 7nm. With fully equipped fabs expected to rise into the plus-$10 billion range over the next few process nodes, and each new process shrink jam-packed with a multitude of new problems, the momentum for continuing to shrink features appears to be slowing down. Technically, it’s possible to shrink transistor... » read more

3D-IC Standardization Progress Continues
By James Amano - 14 Nov, 2013 - Comments: 1

Since its formation in December 2010, the SEMI 3DS-IC Standards Committee has made significant progress in establishing key standards in areas such as TSV metrology, glass carrier wafers, and terminology. The committee’s two newest standards are SEMI 3D6-0913 - Guide for Chemical Mechanical Planarization (CMP) and Micro-Bump Processes for Frontside Through Silicon Via (TSV) Integration, and S... » read more

From DFM To IFM
By Ed Sperling - 14 Nov, 2013 - Comments: 0

For the past decade the bridge between design and manufacturing was called, appropriately enough, design for manufacturing. DFM tools, which by nature cross boundaries of what previously were discrete segments in the semiconductor flow, are now critical for complex designs. They allow design teams to check early in the design process whether chips will yield sufficiently and to incorporate rule... » read more

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