tag: 3D-IC

The Internet Of Cores
By Brian Bailey - 20 Nov, 2014 - Comments: 0

Ever since the birth of the third-party [getkc id="43" comment="IP"] market, there has been a desire for plug-and-play compatibility between cores. Part of the value proposition of reuse is that a block has been used before, and has been verified and validated by having been implemented in silicon. By re-using the core, many of these tasks no longer land on the [getkc id="81" kc_name="SoC"] dev... » read more

Future Directions Unknown
By Ed Sperling - 13 Nov, 2014 - Comments: 0

The semiconductor industry has been on cruise control when it comes to shrinking features, but as process technology progresses to 10nm and 7nm there will be some significant changes. For one thing, the cost per new design will continue to rise, which means only the largest companies with the biggest market opportunity will be able to invest at the leading-edge nodes. Chips for mobile phones... » read more

The Week In Review: Design
By Ed Sperling - 24 Oct, 2014 - Comments: 0

IP Cadence rolled out a portfolio of stacked die memory verification IP to support Wide I/O-2, Hybrid Memory Cube, high-bandwidth memory, and DDR4-3DS. Included are direct memory access for read, write, save, preload and comparison of memory contents, assertions, error configurability, and a built-in address manager. ARM rolled out additions to its enterprise-class SoC interconnects for qua... » read more

Balancing The Cost Of Test
By Brian Bailey - 23 Oct, 2014 - Comments: 0

As semiconductor devices became larger and more complex, the cost of [getkc id="174" kc_name="test"] increased. Testers were large pieces of capital equipment designed to execute functional vectors at-speed and the technology being used had to keep up with increasing demands placed on them. Because of this, the cost of test did not decrease in the way that other high-tech equipment did. Around ... » read more

Why Is My Device Better Than Yours?
By Ed Sperling - 23 Oct, 2014 - Comments: 0

Differentiation is becoming a big problem in the semiconductor industry with far-reaching implications that extend well beyond just chips. The debate over the future of [getkc id="74" comment="Moore's Law"] is well known, but it's just one element in a growing list that will make it much harder for chip companies, IP vendors and even software developers to stand out from the pack. And withou... » read more

Litho Options Sparse After 10nm
By Mark LaPedus - 16 Oct, 2014 - Comments: 0

Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in [getkc id="80" comment="lithography"], chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm. So now, chipmakers are focusing on the lithography options for 7nm. As before, the options include the usual suspects—[gettech id="... » read more

One-On-One: Mike Muller
By Ed Sperling - 13 Oct, 2014 - Comments: 0

SE: What happens with memory, where access is more localized? Muller: Hybrid memory cube is one approach. HBM is another. ARM is chairing an IEEE standards group for a next-gen memory interface to make sure we build memories that fit mobile as well as networking and classic servers. Whereas in the past, memories were driven from the performance, we need to make the power scales with the band... » read more

Memory Directions Uncertain
By Brian Bailey - 09 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down with a panel of experts to find out what is happening in world of memories. Taking part in the discussion are [getperson id="11073" comment="Charlie Cheng"], chief executive officer at [getentity id="22135" e_name="Kilopass Technology"]; Navraj Nandra, senior director of marketing for Analog/Mixed signal IP, embedded memories and logic libraries at [getentity ... » read more

Multi-Die Packaging Gains Steam
By Si2 - 06 Oct, 2014 - Comments: 0

By Herb Reiter Many readers will be familiar with my extensive background and focus in the emerging field of 3D IC technology, including both 3D stacked die and 2.5 interposer design flows. Now, I am excited to bring my expertise and passion to Silicon Integration Initiative (Si2), where I am now Director of 3D Programs, helping Si2’s members in the Open3D Technical Advisory Board develop pr... » read more

More Than Moore
By Ed Sperling - 01 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

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