tag: 3D-IC

The Week In Review: Sept. 20
By Ed Sperling - 20 Sep, 2013 - Comments: 0

By Ed Sperling It’s reference flow update time as TSMC prepares to roll out both finFETs and stacked die capabilities, and advanced capabilities at 20nm. The foundry updated its reference flows to include tools and IP from all of the Big Three EDA companies. It added Mentor Graphics’ place and route and DFM tools in its 16nm finFET reference flow, and added a slew of Mentor tools, inclu... » read more

Stacking The Deck
By Javier DeLaCruz - 22 Aug, 2013 - Comments: 0

By Javier DeLaCruz The pinnacle of system-on-chip has passed. There are several dynamics that are moving the industry away from the SoC philosophy that was so popular just a few short years ago. One of the significant factors is that the cost per gate for CMOS nodes below 28nm is rising for the first time in the history of our industry. Another critical factor is the emergence of through-silic... » read more

Stacking The Deck
By Javier DeLaCruz - 22 Aug, 2013 - Comments: 0

By Javier DeLaCruz The pinnacle of system-on-chip has passed. There are several dynamics that are moving the industry away from the SoC philosophy that was so popular just a few short years ago. One of the significant factors is that the cost per gate for CMOS nodes below 28nm is rising for the first time in the history of our industry. Another critical factor is the emergence of through-silic... » read more

ATE Market Changes With The Times
By Jeff Chappell - 15 Aug, 2013 - Comments: 0

By Jeff Chappell A declining PC market in recent years coupled with the continuing growth of mobile phones and tablets has meant changes throughout the semiconductor supply chain, and automated test equipment is no exception. For example, a decade ago memory test—namely DRAM—was a large market compared with that of nascent system-on-a-chip (SoC) testing. In fact, at the time some test e... » read more

Materials, Software And Techniques
By Ed Sperling - 26 Jul, 2013 - Comments: 0

The future of advanced semiconductor technology is about to split evenly into three different areas. On the leading edge of manufacturing, Applied Materials CEO Mike Splinter called it correctly—it’s all about materials. Just shrinking features isn’t buying much anymore. In fact, at advanced nodes, with extra margin built into designs, it frequently doesn’t buy anything except extra ... » read more

3D IC Supply Chain: Still Under Construction
By Barbara Jorgensen - 25 Jul, 2013 - Comments: 1

By Barbara Jorgensen and Ed Sperling Stacked die, which promise high levels of integration, a tiny footprint, energy conservation and blinding speed, still have some big hurdles to overcome. Cost, packaging and manufacturability continue to make steady progress, with test chips being produced by all of the major foundries. But in a disaggregated ecosystem, the supply chain remains a big st... » read more

Experts At The Table: Who Pays For Low Power?
By Ed Sperling - 11 Jul, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the cost of low power with Fadi Gebara, research staff member for IBM’s Austin Research Lab; David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Aveek Sarkar, vice president of product engineering and support at Apache Design; and Tim Whitfield, director o... » read more

The Rise Of Semiconductor IP Subsystems
By Various Writers - 11 Jul, 2013 - Comments: 0

The semiconductor IP (SIP) market arose when SIP vendors created IP functions that mirrored those found in the discrete semiconductor market and made those functions available to SoC designers in the form of hard or soft SIP blocks. As the SoC and SIP markets evolved, it was a natural evolution that many discrete SIP functions be converged into larger blocks that mimic system-level functions (i... » read more

Dealing With New Bottlenecks
By Ed Sperling - 11 Jul, 2013 - Comments: 0

By Ed Sperling While the number of options for improving efficiency and performance in designs continues to increase, the number of challenges in getting chips at advanced process nodes out the door is increasing, too. Thinner wires, routing congestion, more power domains, IP integration and lithography issues are conspiring to make design much more difficult than in the past. So why aren�... » read more

New Approaches To Better Performance And Lower Power
By Ed Sperling - 11 Jul, 2013 - Comments: 0

By Ed Sperling Until 90nm, every feature shrink and rev of Moore’s Law included a side benefit of better power and performance. After that, improvements involved everything from different back-end processes to copper interconnects and transistor structures. But from 20nm onward, the future will rest with a combination of new materials, new architectures and new packaging approaches—and som... » read more

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