tag: 3nm

Aging Problems At 5nm And Below
By Brian Bailey - 11 Jun, 2020 - Comments: 3

The mechanisms that cause aging in semiconductors have been known for a long time, but the concept did not concern most people because the expected lifetime of parts was far longer than their intended deployment in the field. In a short period of time, all of that has changed. As device geometries have become smaller, the issue has become more significant. At 5nm, it becomes an essential par... » read more

EUV’s Uncertain Future At 3nm And Below
By Mark LaPedus - 21 May, 2020 - Comments: 5

Several foundries have moved extreme ultraviolet (EUV) lithography into production at both 7nm and 5nm, but now the industry is preparing for the next phase of the technology at 3nm and beyond. In R&D, the industry is developing new EUV scanners, masks and resists for the next nodes. 3nm is slated for 2022, followed by 2nm a year or two later. Nonetheless, it will require massive funding... » read more

Challenges In Stacking, Shrinking And Inspecting Next-Gen Chips
By Ed Sperling and Mark LaPedus - 21 May, 2020 - Comments: 0

Rick Gottscho, CTO of Lam Research, sat down with Semiconductor Engineering to discuss memory and equipment scaling, new market demands, and changes in manufacturing being driven by cost, new technologies, and the application of machine learning. What follows are excerpts of that conversation. SE: We have a lot of different memory technologies coming to market. What's the impact of that? ... » read more

An Inside Look At Testing’s Leading Edge
By Ed Sperling - 12 May, 2020 - Comments: 0

Mike Slessor, president and CEO of FormFactor, sat down with Semiconductor Engineering to discuss testing of AI and 5G chips, and why getting power into a chip for testing is becoming more difficult at each new node. SE: How does test change with AI chips, where you've got massive numbers of accelerators and processors developed at 7 and 5nm? Slessor: A lot of the AI stuff that we've been... » read more

A Node Too Far?
By Ed Sperling - 23 Apr, 2020 - Comments: 1

Physics is an unforgiving master. While the semiconductor industry has been actively developing new transistor structures, new materials for interconnects and lining trenches, and new approaches to alleviate congestion at the lowest metal levels, it also has been playing an accelerating game of Whac-a-Mole. Whenever a problem pops up, the solution to that problem is never complete and more prob... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 17 Apr, 2020 - Comments: 0

Chipmakers TSMC posted mixed results for the quarter, although there was a capital spending surprise. “It maintained its 2020 capex at $15B-$16B despite smartphone softness, primarily to support a strong 5nm ramp, led by demand from 5G and HPC customers,” said Weston Twigg, an analyst at KeyBanc, in a research note. “Despite lowering its industry outlook, TSMC still expects to grow its o... » read more

Scaling At The Angstrom Level
By Ed Sperling - 16 Apr, 2020 - Comments: 0

It now appears likely that 2nm will happen, and possibly the next node or two beyond that. What isn't clear is what those chips will be used for, by whom, and what they ultimately will look like. The uncertainty isn't about the technical challenges. The semiconductor industry understands the implications of every step of the manufacturing process down to the sub-nanometer level, including ho... » read more

Making Chips At 3nm And Beyond
By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

Big Changes In Tiny Interconnects
By Ed Sperling - 16 Apr, 2020 - Comments: 1

One of the fundamental components of a semiconductor, the interconnect, is undergoing radical changes as chips scale below 7nm. Some of the most pronounced shifts are occurring at the lowest metal layers. As more and smaller transistors are packed onto a die, and as more data is processed and moved both on and off a chip or across a package, the materials used to make those interconnects, th... » read more

Redefining Device Failures
By Ed Sperling - 07 Apr, 2020 - Comments: 0

Can a 5nm or 3nm chip really perform to spec over a couple decades? The answer is yes, but not using traditional approaches for designing, manufacturing or testing those chips. At the next few process nodes, all the workarounds and solutions that have been developed since 45nm don't necessarily apply. In the early finFET processes, for example, the new transistor structure provided a huge im... » read more

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