tag: 3nm

What’s Next In AI, Chips And Masks
By Mark LaPedus - 19 Nov, 2020 - Comments: 0

Aki Fujimura, chief executive of D2S, sat down with Semiconductor Engineering to talk about AI and Moore’s Law, lithography, and photomask technologies. What follows are excerpts of that conversation. SE: In the eBeam Initiative’s recent Luminary Survey, the participants had some interesting observations about the outlook for the photomask market. What were those observations? Fujimur... » read more

Rethinking The Scaling Mantra
By Ed Sperling - 26 Oct, 2020 - Comments: 0

What makes a new chip better than a previous version, or a competitor's version, has been changing for some time. In most cases the key metrics are still performance and power, but what works for one application or use case increasingly is different from another. Advancements are rarely tied just to process nodes these days. Even the most die-hard proponents of Moore's Law recognize that the... » read more

Regaining The Edge In U.S. Chip Manufacturing
By Mark LaPedus & Ann Steffora Mutschler - 26 Oct, 2020 - Comments: 16

The United States is developing new strategies to prevent it from falling further behind Korea, Taiwan, and perhaps even China in semiconductor manufacturing, as trade tensions and national security concerns continue to grow. For years, the U.S. has been a leader in the development of new chip products like GPUs and microprocessors. But from a chip manufacturing standpoint, the U.S. is losin... » read more

Productivity Keeping Pace With Complexity
By Brian Bailey - 24 Sep, 2020 - Comments: 0

Designs have become larger and more complex and yet design time has shortened, but team sizes remain essentially flat. Does this show that productivity is keeping pace with complexity for everyone? The answer appears to be yes, at least for now, for a multitude of reasons. More design and IP reuse is using more and larger IP blocks and subsystems. In addition, the tools are improving, and mo... » read more

Custom Designs, Custom Problems
By Ed Sperling - 16 Sep, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

Challenges At 3/2nm
By Ed Sperling - 15 Sep, 2020 - Comments: 0

David Fried, vice president of computational products at Lam Research, talks about issues at upcoming process nodes, the move to EUV lithography and nanosheet transistors, and how process variation can affect yield and device performance. » read more

New Architectures, Much Faster Chips
By Ed Sperling and Ann Mutschler - 31 Aug, 2020 - Comments: 0

The chip industry is making progress in multiple physical dimensions and with multiple architectural approaches, setting the stage for huge performance increases based on more modular and heterogeneous designs, new advanced packaging options, and continued scaling of digital logic for at least a couple more process nodes. A number of these changes have been discussed in recent conferences. I... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 28 Aug, 2020 - Comments: 0

Pervasive computing — data center, edge, IoT Marvell is working on silicon for the data infrastructure market using TSMC’s 5nm process node. Marvell says it has multiple designs already under contract for its 5nm portfolio across the carrier, enterprise, automotive, and data center markets. The first products are sampling by the end of next year.  Ansys’ multiphysics signoff tools, R... » read more

Finding Defects With E-Beam Inspection
By Mark LaPedus - 20 Aug, 2020 - Comments: 0

Several companies are developing or shipping next-generation e-beam inspection systems in an effort to reduce defects in advanced logic and memory chips. Vendors are taking two approaches with these new e-beam inspection systems. One is a more traditional approach, which uses a single-beam e-beam system. Others, meanwhile, are developing newer multi-beam technology. Both approaches have thei... » read more

Power And Performance Optimization At 7/5/3nm
By Ed Sperling - 13 Aug, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

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