BEOL Issues At 10nm And 7nm (part 2)


Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

Architect Specs Harder To Follow


Interpreting and implementing architects' specifications is getting harder at each new process node, which is creating problems throughout the design flow, into manufacturing, and sometimes even post-production. Rising complexity and difficulties in scaling have pushed much more of the burden onto architects to deal with everything from complex power schemes, new packaging approaches, and to... » read more

Foundries See Mixed Future


Amid a tumultuous business environment, the silicon foundry industry is projected to see steady growth in a number of process segments in 2017. As in past years, the foundry market is expected to grow faster than the overall IC industry in 2017. But at the same time, the IC industry—the foundry customer base—continues to witness a frenetic wave of merger and acquisition activity. Basical... » read more

Uncertainty Grows For 5nm, 3nm


As several chipmakers ramp up their 10nm finFET processes, with 7nm just around the corner, R&D has begun for 5nm and beyond. In fact, some are already moving full speed ahead in the arena. [getentity id="22586" comment="TSMC"] recently announced plans to build a new fab in Taiwan at a cost of $15.7 billion. The proposed fab is targeted to manufacture TSMC’s 5nm and 3nm processes, whic... » read more

Morphing Moore’s Law


In 1965, Gordon Moore defined a timetable for doubling the number of transistors on a piece of silicon every two years. The law, as he originally defined it, is now hopelessly outdated. Any attempts to apply it to the most advanced chips today are a stretch at best, and complete fiction at worst. No one is on a two-year cadence between process nodes anymore—not even Intel. In fact, no one ... » read more

Etching Technology Advances


Let’s get really, really small. That directive from leading semiconductor companies and their customers is forcing the whole semiconductor supply chain to come up with new ways to design and manufacture ever-shrinking dimensions for chips. The current push is to 10nm and 7nm, but R&D into 5nm and 3nm is already underway. To put this in perspective, there are roughly two silicon atom... » read more

Inside Advanced Patterning


Prabu Raja, group vice president and general manager for the Patterning and Packaging Group at [getentity id="22817" e_name="Applied Materials"], sat down with Semiconductor Engineering to discuss the trends in patterning, selective processes and other topics. Raja is also a fellow at Applied Materials. What follows are excerpts of that conversion. SE: From your standpoint, what are the big... » read more

BEOL Issues At 10nm And 7nm (Part 1)


Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

BEOL Barricades Ahead


Coventor recently assembled an expert panel at IEDM 2016, to discuss changes to BEOL process technology that would be needed to continue dimensional scaling to 7 nm and lower. Among the questions posed to panelists: What is BEOL? Where does it begin and end? Are there fundamental limits to interconnect processes? How much longer can we continue to use current interconnect processes and ... » read more

Design Convergence For 7nm Chips Needs Big Data-Driven Multi-Physics Optimization


Advancements in silicon process technologies are enabling companies to deliver products with faster performance, lower power and greater functionality. These benefits are especially attractive for chip manufacturers servicing markets such as high-end mobile and enterprise computing. However, the cost in terms of both dollars and resources associated with bringing 7-nanometer (nm) finFET-based s... » read more

← Older posts Newer posts →