tag: AMD

Betting On Glass TSVs
By Ed Sperling - 22 Sep, 2011 - Comments: 0

By Ed Sperling There are two big issues when it comes to through-silicon vias. One involves cost. The second involves heat—in particular, how to get heat out of a stacked die and what the thermal coefficient of the TSV will be to make sure it expands at a rate consistent with the SoCs in a package. To address these issues, System-Level Design caught up with Rao Tummala, professor of elect... » read more

More Analog Needed For Multicore SoCs
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Mike Demler Minimizing on-chip power consumption continues to be one of the greatest challenges facing SoC designers. Everyone who owns a cell phone has undoubtedly seen the effect on limited battery life firsthand, but the impact on the unseen compute servers in “the cloud” is even more severe, making total electrical operating costs greater than the hardware expense, according to AMD ... » read more

The Big Picture
By Ed Sperling - 22 Jul, 2011 - Comments: 0

Business is booming for the makers of processors. Intel posted its five consecutive record quarter, AMD turned a profit, Tensilica shipped its billionth DSP, ARM and MIPS are both reporting strong earnings. So what’s changed? There are several distinct trends driving this upbeat mood: The replacement cycle. After years of putting off purchases through a prolonged and deep downturn, com... » read more

Tri-Gate’s Fallout
By Ed Sperling - 26 May, 2011 - Comments: 0

By David Lammers Intel Corp. dropped a rock into the pond of transistor technology when it announced its 22nm tri-gate technology in San Francisco earlier this month. The ripples continue to move out from that event, with impacts on IDMs, foundries, and fabless semiconductor companies being closely studied. Now that Intel has come out of the closet with its tri-gate technology, “the found... » read more

The Enterprise Effect
By Ed Sperling - 24 Feb, 2011 - Comments: 0

By Pallab Chatterjee In the enterprise it’s all about speed and power—as in more speed and less power—and those changes are forcing shifts in the chip architectures as well as the processes used to develop those chips. At the Linley Data Center Conference the next generation of network control chips were discussed. The keys for the new networks are 10G data lanes to be used with 10G/4... » read more

Material Effects: Trading Performance For Power
By Ed Sperling - 13 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler Power impacts everything, even when it comes to semiconductor manufacturing materials. While bulk CMOS technology still reigns supreme, there are a number of advanced materials being suggested as replacements when it runs out of steam at around 15nm, including silicon on insulator (SOI)—particularly in combination with FinFET multigate structures on SOI—silicon ge... » read more

Bridging IP With Verification Standards
By Ann Mutschler - 21 Oct, 2010 - Comments: 0

By Ann Steffora Mutschler Standards body Accellera is sounding the gong to summon all verification IP providers to check out its efforts in connection with IP-XACT -- IEEE 1685, "Standard for IP-XACT, Standard Structure for Packaging, Integrating and Re-Using IP Within Tool-Flows” – with verification IP. The IP-XACT technical committee has been busy over the past year. Formerly an effor... » read more

Storm Before The Calm
By Ed Sperling - 17 Sep, 2010 - Comments: 0

The announcements out of ARM and Intel over the past couple week—and presumably from rivals AMD, MIPS and even Nvidia in coming weeks—are more than just a struggle for one-upmanship. The goal is much more far-reaching and the stakes are significantly higher than who has the fastest processor or core or even the lowest-power version. In the past year there has been a massive push to expan... » read more

Betting On 3D
By Ed Sperling - 26 Aug, 2010 - Comments: 0

The continuation of Moore’s Law appears less in doubt than ever. Companies such as Intel, ST, AMD (via GlobalFoundries) and IBM are testing FinFETS and ETSOI and work is being done on the back end to ensure that these new structures can be manufactured with sufficient yield. What’s changed, though, is the resistance by other companies to the progression of Moore’s Law. There is no long... » read more

Power Or Performance?
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Pallab Chatterjee Most microprocessors have shifted to new small geometry processes in order to be the most efficient at power and high performance. However there is always a trade-off between power, performance and area (PPA) for semiconductors, and this is especially relevant for processors. In the current design space, processors are created as general-purpose products, but they are gene... » read more

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