Faster Analog Design Closure With Early Parasitic Analysis Flow – Part 1

By Synopsys - 22 Sep, 2021 - Comments: 0

In part 1 of this series, Denis Goinard, Director of Engineering at Synopsys, discusses how Synopsys provides a unified workflow to accurately estimate, measure, extract and simulate parasitics by bringing signoff tools into the design process, enabling faster design convergence. Click here to play the video. Note: This is a Synopsys 'video white paper.' For more video white papers, click h... » read more

System-In-Package Thrives In The Shadows

By Mark LaPedus - 16 Sep, 2021 - Comments: 0

IC packaging continues to play a big role in the development of new electronic products, particularly with system-in-package (SiP), a successful approach that continues to gain momentum — but mostly under the radar because it adds a competitive edge. With a SiP, several chips and other components are integrated into a package, enabling it to function as an electronic system or sub-system. ... » read more

Wrestling With Analog At 3nm

By Brian Bailey - 09 Sep, 2021 - Comments: 0

Analog engineers are facing big challenges at 3nm, forcing them to come up with creative solutions to a widening set of issues at each new process node. Still, these problems must be addressed, because no digital chip will work without at least some analog circuitry. As fabrication technologies shrink, digital logic improves in some combination of power, performance, and area. The process te... » read more

40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors

By Technical Paper Link - 31 Aug, 2021 - Comments: 0

Abstract: "This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide�... » read more

The Evolving Landscape Of SoC Vulnerabilities And Analog Threats

By Siemens EDA - 04 Aug, 2021 - Comments: 0

SoC integrators know that a software-only chip security plan leaves devices open to attack. The more effective way to thwart hackers is to combat both digital and analog threats by incorporating security-focused hardware modules built into the core machine design. This paper describes sources of vulnerabilities to cyber attacks and what infrastructure is needed to secure against them. The So... » read more

ASIC/IC Verification Trends With A Focus On Factors Of Silicon Success

By Harry Foster - 08 Jul, 2021 - Comments: 0

At long last we come to the final installment of our four-part series presenting the findings of the Wilson Research Group Functional Verification 2020 study. In this article we discuss verification trends in IC/ASIC language and library adoption, low power management, and verification effectiveness. We then take a deeper dive into two somewhat surprising phenomena revealed in the data: the ... » read more

‘Hug The Debug’ – Before It’s Too Late

By Sumit Vishwakarma - 01 Jul, 2021 - Comments: 0

Though the term “shift-left” originated in the software industry, its importance is often cited in the hardware (semiconductor) industry where the end-product (chip) costs are skyrocketing. The increase in cost is driven by a global chip shortage, especially in the automotive industry. Manufacturing a robust chip is a long, iterative process that may require many re-spins. Shift-left refers... » read more

High Thermal Die-Attach Paste Development For Analog Circuits

By Amkor - 16 Jun, 2021 - Comments: 0

In recent years, various die attach (DA) materials have been developed to cope with the higher power dissipation requirements of semiconductor devices. DA materials based on metals such as solder or sintered silver (Ag) are used for very high heat generating power devices. While they show outstanding thermal performance, the mechanical properties of these materials are less than ideal. This lim... » read more

Monitoring Performance From Inside A Chip

By Ed Sperling - 01 Jun, 2021 - Comments: 0

Deep data, which is generated inside the chip rather than externally, is becoming more critical at each new process node and in advanced packages. Uzi Baruch, chief strategy officer at proteanTecs, talks with Semiconductor Engineering about using that data to identify potential problems before they result in failures in the field, and why it's essential to monitor these devices throughout their... » read more

Virtuoso ADE Assembler

By Cadence - 26 May, 2021 - Comments: 0

Cadence Virtuoso ADE Assembler is an advanced design and simulation environment that extends the capabilities of Virtuoso ADE Explorer, adding all the tests needed to fully verify a design over all operational, process, and environmental conditions. As more analysis is required, users can take incremental advantage of the Virtuoso Variation Option to do more advanced statistical analysis on the... » read more

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tag: analog

Faster Analog Design Closure With Early Parasitic Analysis Flow – Part 1

System-In-Package Thrives In The Shadows

Wrestling With Analog At 3nm

40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors

The Evolving Landscape Of SoC Vulnerabilities And Analog Threats

ASIC/IC Verification Trends With A Focus On Factors Of Silicon Success

‘Hug The Debug’ – Before It’s Too Late

High Thermal Die-Attach Paste Development For Analog Circuits

Monitoring Performance From Inside A Chip

Virtuoso ADE Assembler

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