tag: BEOL

7nm Fab Challenges
By Mark LaPedus - 21 Apr, 2016 - Comments: 3

Leading-edge foundry vendors have made the challenging transition from traditional planar processes into the finFET transistor era. The first [getkc id="185" kc_name="finFETs"] were based on the 22nm node, and now the industry is ramping up 16nm/14nm technologies. Going forward, the question is how far the finFET can be scaled. In fact, 10nm finFETs from Samsung are expected to ramp by ye... » read more

Insider’s Guide To Fab Technology
By Mark LaPedus - 21 Apr, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss fab technology with Matt Paggi, vice president of advanced technology development at GlobalFoundries. What follows are excerpts of that conversation. SE: What’s driving demand for semiconductors today? Paggi: You are aware of what the worldwide semiconductor revenue growth is this year. There are peaks and valleys in the worldwide semiconduc... » read more

Inside Process Technology
By Mark LaPedus - 21 Apr, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss the foundry business, memory, process technology, lithography and other topics with David Fried, chief technology officer at [getentity id="22210" e_name="Coventor"], a supplier of predictive modeling tools. What follows are excerpts of that conversation. SE: Chipmakers are ramping up 16nm/14nm finFETs today, with 10nm and 7nm finFETs just around... » read more

Pain Points At 7nm
By Ed Sperling - 24 Mar, 2016 - Comments: 3

Early work has begun on 7nm. Process technology has progressed to the point where IP and tools are being qualified. There is still a long way to go. But as companies begin engaging with foundries on this process node—[getentity id="22586" comment="TSMC"] is talking publicly about it, but [getentity id="22846" e_name="Intel"], [getentity id="22819" comment="GlobalFoundries"] and [getentity ... » read more

Interconnect Challenges Grow
By Mark LaPedus - 20 Aug, 2015 - Comments: 1

It’s becoming apparent that traditional chip scaling is slowing down. The 16nm/14nm logic node took longer than expected to unfold. And the 10nm node and beyond could suffer the same fate. So what’s the main cause? It’s hard to pinpoint the problem, although many blame the issues on lithography. But what could eventually hold up the scaling train, and undo Moore’s Law, is arguably t... » read more

Fab Issues At 7nm And 5nm
By Mark LaPedus - 23 Jul, 2015 - Comments: 2

The race toward the 7nm logic node officially kicked off in July, when IBM Research, GlobalFoundries and Samsung jointly rolled out what the companies claim are the industry’s first 7nm test chips with functional transistors. They're not alone, of course. Intel and TSMC also are racing separately to develop 7nm technology. And in the R&D labs, chipmakers also are working on technologies f... » read more

The Fill Ecosystem Evolves Again
By Jeff Wilson - 23 Jul, 2015 - Comments: 0

Several years ago, we wrote about the ecosystem of fill, and how 20nm technology required a much tighter relationship between the foundry, designers and EDA vendors. While the players remain the same, there have been some interesting shifts in fill techniques and usage as designers move to even-smaller technologies. What continues with each node is the additional complexity of the design flo... » read more

Addressing Thin Film Thickness Metrology Challenges Of 14nm BEOL Layers
By KLA - 21 May, 2015 - Comments: 0

This paper describes a method to effectively monitor the film stack at different metal CMP process steps using a spectroscopic ellipsometer metrology tool. By proper modeling of the Cu dispersion and simulating the underlayer film information underneath the Cu pad, a single measurement recipe was developed which can be used to monitor each process step in the metal CMP process with stable and r... » read more

Extending The Hardmask
By Mark LaPedus - 19 May, 2015 - Comments: 0

In chip production, the backend-of-the-line (BEOL) is where the critical interconnects are formed within a device. Interconnects—those tiny wiring schemes in devices—are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the resistance-capacitance (RC) delay in chips. “The scaling roadblocks that the interconnect faces need to ... » read more

Will 7nm And 5nm Really Happen?
By Mark LaPedus - 14 Jul, 2014 - Comments: 2

Today’s silicon-based finFETs could run out of steam at 10nm. If or when chipmakers move beyond 10nm, IC vendors will require a new transistor architecture. III-V finFETs, gate-all-around FETs, quantum well finFETs, SOI finFETs and vertical nanowires are just a few of the future transistor candidates at 7nm and 5nm. Technically, it’s possible to manufacture the transistor portions of the... » read more

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