Blog Review: June 14


Synopsys' Richard Solomon and Gary Ruggles examine the Compute Express Link (CXL) protocol and how it could unlock new ways of doing computing such as enabling efficient heterogeneous computing architectures, accelerating data-intensive workloads, and facilitating advanced real-time analytics. Cadence's Andre Baguenie explains how to convert an electrical signal to a logic value using the Ve... » read more

Programming Processors In Heterogeneous Architectures


Programming processors is becoming more complicated as more and different types of processing elements are included in the same architecture. While systems architects may revel in the number of options available for improving power, performance, and area, the challenge of programming functionality and making it all work together is turning out to be a major challenge. It involves multiple pr... » read more

Exploring The World Of Flash Memory: Serial, Dual, Quad, And Octal Interface


By Dharini SubashChandran and Manoj Kachadiya In the world of digital data storage, flash memory has become an indispensable technology. Flash memory devices are non-volatile storage solutions that can retain data even without power. They are widely used in various applications, including smartphones, digital cameras, USB drives, and solid-state drives (SSDs). In this blog post, we will delv... » read more

EDA’s Role Grows For Preventing And Identifying Failures


The front end of design is becoming more tightly integrated with the back end of manufacturing, driven by the rising cost and impact of failures in advanced chips and critical applications. Ironically, the starting point for this shift is failure analysis (FA), which typically happens when a device fails to yield, or worse, when it is returned due to some problem. In production, that leads t... » read more

Blog Review: June 7


Synopsys' Kenneth Larsen and Powerchip's S.Z. Chang explore wafer-on-wafer (WoW) and chip-on-wafer (CoW), 3D hybrid bonding schemes that can be used to stack memory on logic with shorter signal transmission distance at no wasted power and more interconnect and bandwidth density. In a podcast, Siemens' Conor Peick, Nand Kochhar, and Mark Sampson chat about how companies can address growing co... » read more

Week In Review: Auto, Security, Pervasive Computing


AI predictions and announcements filled the news this week, including a statement from the Center for AI Safety that was signed by some top AI execs — including Sam Altman, CEO of OpenAI — warning that uncontrolled AI could end up smarter than us and lead to our extinction. Foxconn estimates its artificial intelligence server revenue will double this year with the popularity of generative A... » read more

What Is Zonal Architecture? And Why Is it Upending the Automotive Supply Chain?


Over the last few years, the basic architecture of how a vehicle is put together has changed a lot. This has also resulted in a change in how the automotive supply chain is put together, too. The traditional ECU-based architecture and the automobile supply chain Historically, vehicles have been put together like the picture on the left in the above diagram. Vehicles could have as many a... » read more

How Many Sensors For Autonomous Driving?


With the cost of sensors ranging from $15 to $1,000, carmakers are beginning to question how many sensors are needed for vehicles to be fully autonomous at least part of the time. Those sensors are used to collect data about the surrounding environment, and they include image, lidar, radar, ultrasonic, and thermal sensors. One type of sensor is not sufficient, because each has its limitation... » read more

Blog Review: May 31


Cadence's Moshik Rubin looks at how the Portable Test and Stimulus Standard (PSS) is finding new use cases in ATE production test by enabling creation of a rich set of functional test scenarios in a reusable way. Synopsys' LJ Chen and Dana Neustadter check out the latest version of the Universal Flash Storage (UFS) standard, which doubles the data transfer rate of the preceding UFS 3.1 solut... » read more

Software-Defined Hardware Architectures


Hardware/software co-design has been a goal for several decades, but success has been limited. More recently, progress has been made in optimizing a processor as well as the addition of accelerators for a given software workload. While those two techniques can produce incredible gains, it is not enough. With increasing demands being placed on all types of processing, single-processor solutio... » read more

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