tag: Cadence

IC Stresses Affect Reliability At Advanced Nodes
By Ann Mutschler - 08 Dec, 2022 - Comments: 1

Thermal-induced stress is now one of the leading causes of transistor failures, and it is becoming a top focus for chipmakers as more and different kinds of chips and materials are packaged together for safety- and mission-critical applications. The causes of stress are numerous. In heterogeneous packages, it can stem from multiple components composed of different materials. “These materia... » read more

Challenges With Adaptive Control
By Brian Bailey - 08 Dec, 2022 - Comments: 0

Historically, the performance and power consumption of a system was controlled by what could be done at design time, but chips today are becoming a lot more adaptive. This has become a necessity for cutting edge nodes, but also provides a lot of additional benefits at the expense of greater complexity and verification challenges. Design margins are a tradeoff between performance and yield. C... » read more

Advanced Auto-Routing For TSMC InFO Technologies
By Paul McLellan - 08 Dec, 2022 - Comments: 0

At the recent TSMC OIP Symposium, John Park presented 'Advanced Auto-Routing for TSMC InFO Technologies.' InFO stands for "integrated fanout" and is the lower performance, lower complexity technology for advanced packaging. For details of TSMC's whole packaging portfolio, see my post TSMC OIP: 3DFabric Alliance and 3Dblox. Here's the slide TSMC presented from that presentation on InFO. As you... » read more

Blog Review: Dec. 7
By Jesse Allen - 07 Dec, 2022 - Comments: 0

Siemens EDA's Harry Foster looks at the continual maturing of FPGA functional verification processes through increasing adoption of various simulation-based and formal verification techniques. Synopsys' Stewart Williams introduces the Scalable Open Architecture for Embedded Edge (SOAFEE) project and how it can make automotive software development, testing, virtual prototyping, and validation... » read more

Tensilica DSP Code Generation Toolbox With MATLAB/Simulink
By Cadence - 07 Dec, 2022 - Comments: 0

MATLAB and Simulink are widely used for modeling and simulating real-time dynamical systems. To verify the performance of MATLAB/Simulink models of these systems in a real-time application, MATLAB/Simulink models are converted to embedded C code and executed on a target processor or its equivalent Instruction Set Simulator (ISS). To deploy the generated C code in a processor, the genera... » read more

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 02 Dec, 2022 - Comments: 0

With the European Council’s adoption of its negotiating mandate for the European Chips Act, member states and the Czech Presidency of the Council have reached a critical milestone in supporting Europe’s efforts to advance manufacturing and supply of critical components, while bolstering R&D capacities for development of next-generation semiconductor innovations, according to SEMI. Ch... » read more

Week In Review: Design, Low Power
By Marie C. Baca - 02 Dec, 2022 - Comments: 0

Tools and IP Renesas released a family of configurable clock generators with an internal crystal oscillator for PCIe and networking applications in high-end computing, wired infrastructure and data center equipment. “Timing needs can vary greatly between different applications and equipment, and often change during a product design cycle,” said Zaher Baidas, Vice President of the Timing Pr... » read more

Smart Manufacturing: What’s Needed For The Industrial Intelligence Revolution?
By Ben Gu - 01 Dec, 2022 - Comments: 0

Smart manufacturing – the use of nascent technology within the industrial Internet of things (IIoT) to address traditional manufacturing challenges – is leading a supply chain revolution, resulting in smart, connected, and intelligent environments, capable of self-operation and self-healing. While factory automation has been around for decades, smart manufacturing goes a great deal furth... » read more

Blog Review: Nov. 30
By Jesse Allen - 30 Nov, 2022 - Comments: 0

Cadence's Sangeeta Soni explores how the configuration space for CXL 1.1 and CXL 2.0 varies and discusses newly introduced registers for the CXL-compliant devices and how they are discovered during the CXL enumeration flow. Siemens EDA's Harry Foster continues examining trends in FPGA verification effort by looking at where both design and verification engineers spend their time. Synopsys... » read more

Improving Concurrent Chip Design, Manufacturing, And Test Flows
By Ann Mutschler - 28 Nov, 2022 - Comments: 0

Semiconductor design, manufacturing, and test are becoming much more tightly integrated as the chip industry seeks to optimize designs using fewer engineers, setting the stage for greater efficiencies and potentially lower chip costs without just relying on economies of scale. The glue between these various processes is data, and the chip industry is working to weave together various steps t... » read more

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