Debug Solutions For Designers Accelerate Time To Verification

By Neil Hand - 28 Oct, 2021 - Comments: 0

Complexity continues to explode as designs become larger and more complicated with more functionality and more aggressive expectations. The cost of doing business as usual, for the entire design and verification team, in turn, grows exponentially, in terms of time, effort, and dollars. Fig. 1: Discovering issues later than possible requires more effort to find and fix. (Source: Wilson Rese... » read more

Software-Hardware Co-Design Becomes Real

By Brian Bailey - 27 Sep, 2021 - Comments: 1

For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some of the basics. Hardware/software co-design is essentially a bottom-up process, where hardware is deve... » read more

Hyper-Convergence Is The New Normal For Digital Implementation

By Yudhan Rajoo - 23 Sep, 2021 - Comments: 0

The era of smart-everything has led to a surge in the need for semiconductor devices across a myriad of traditional and novel applications. These applications demand high performance yet energy-efficient compute over blazing-fast networks to service trillions of edge devices that are constantly consuming and generating large amounts of data. This surge has invigorated system architects to innov... » read more

Impact Of GAA Transistors At 3/2nm

By Brian Bailey - 16 Aug, 2021 - Comments: 2

The chip industry is poised for another change in transistor structure as gate-all-around (GAA) FETs replace finFETs at 3nm and below, creating a new set of challenges for design teams that will need to be fully understood and addressed. GAA FETs are considered an evolutionary step from finFETs, but the impact on design flows and tools is still expected to be significant. GAA FETs will offer... » read more

Designing Chips In A ‘Lawless’ Industry

By Ed Sperling - 02 Aug, 2021 - Comments: 2

The guideposts for designing chips are disappearing or becoming less relevant. While engineers today have many more options for customizing a design, they have little direction about what works best for specific applications or what the return on investment will be for those efforts. For chip architects, this is proving to be an embarrassment of riches. However, that design freedom comes wit... » read more

CEO Outlook: More Data, More Integration, Same Deadlines

By Ed Sperling - 24 Jun, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What ... » read more

How To Build A Virtual Electromagnetic Test Environment For Aerospace And Automotive Platforms

By Ansys - 09 Jun, 2021 - Comments: 0

To protect the electromagnetic compatibility (EMC) of complex systems like aircraft and automobiles, you need a full electromagnetic (EM) model. A virtual test environment allows you to assess a design and ensure system-level compatibility before physical testing. This process has been proven to save more than $1 million compared to an approach based solely on testing. Learn how to build a v... » read more

Next-Gen Design Challenges

By Ed Sperling - 20 Apr, 2021 - Comments: 0

As more heterogeneous chips and different types of circuitry are designed into one system, that all needs to be simulated, verified and validated before tape-out. Aveek Sarkar, vice president of engineering at Synopsys, talks with Semiconductor Engineering about the intersection of scale complexity and systemic complexity, the rising number of corners, and the reduced margin with which to buffe... » read more

EDA, IP Revenues Soar

By Ed Sperling - 13 Apr, 2021 - Comments: 1

EDA and IP revenues increased 15.4% to $3.032 billion in Q4 2020, according to a just-released report, with huge increases reported in China and India, and a solid double-digit increase in the Americas. EDA/IP revenue from China increased 66.4% in Q4 EDA/IP compared with the same period in 2019, and for the 2020 calendar year it was up 52.3%. India's spending was up 32% for the quarter. And ... » read more

Startup Funding: September 2020

By Jesse Allen - 01 Oct, 2020 - Comments: 0

It was a good month for startups, with big rounds in automotive, data centers, and AI. A new startup with big backing is taking aim at energy inefficiency in the data center, and another is looking to make the industrial IoT battery-free. SK Hynix founded a new company to analyze semiconductor manufacturing data, and one of China's EV companies sees a massive cash infusion. This month, we look ... » read more

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Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.