tag: chip design

Does EDA Sell Fear?
By Brian Bailey - 24 Feb, 2022 - Comments: 3

I worked in the EDA industry for over 30 years and a common lament I heard was that the EDA industry survived by selling fear. Your new chip will fail if you do not buy the latest tool offering. There always seemed to be a natural dislike for the EDA industry and many users thought the industry overcharged and was unable to innovate. I never quite understood the reasoning. A recent comment, ... » read more

Spreadsheets: Still Valuable, But More Limited
By Brian Bailey - 10 Feb, 2022 - Comments: 1

Spreadsheets have been an invaluable engineering tool for many aspects of semiconductor design and verification, but their inability to handle complexity is squeezing them out of an increasing number of applications. This is raising questions about whether they still have a role, and if so, how large that role will be. There are two sides to this issue. On one side are the users who see them... » read more

The Importance Of Layering Data
By Ed Sperling - 11 Jan, 2022 - Comments: 0

The chip industry generates enormous quantities of data, from design through manufacturing, but much of it is unavailable or incomplete. And even when and where it is available, it is frequently under-utilized. While there has been much work done in terms of establishing traceability and data formats, the cross-pollination of data between companies and between equipment makers at various pro... » read more

Raising The Bar With The Next Generation Of AI For Chip Design
By Synopsys - 22 Nov, 2021 - Comments: 0

The semiconductor industry is enjoying renewed growth despite chip shortages plaguing everything from cars to kitchen appliances. But while the chips themselves continue to get faster and smarter, the chip design process itself hasn’t changed that much in 20+ years. It typically takes 2-3 years to design a chip with a large engineering team and tens or hundreds of millions of dollars to get a... » read more

Debug Solutions For Designers Accelerate Time To Verification
By Neil Hand - 28 Oct, 2021 - Comments: 0

Complexity continues to explode as designs become larger and more complicated with more functionality and more aggressive expectations. The cost of doing business as usual, for the entire design and verification team, in turn, grows exponentially, in terms of time, effort, and dollars. Fig. 1: Discovering issues later than possible requires more effort to find and fix. (Source: Wilson Rese... » read more

Software-Hardware Co-Design Becomes Real
By Brian Bailey - 27 Sep, 2021 - Comments: 1

For the past 20 years, the industry has sought to deploy hardware/software co-design concepts. While it is making progress, software/hardware co-design appears to have a much brighter future. In order to understand the distinction between the two approaches, it is important to define some of the basics. Hardware/software co-design is essentially a bottom-up process, where hardware is deve... » read more

Hyper-Convergence Is The New Normal For Digital Implementation
By Yudhan Rajoo - 23 Sep, 2021 - Comments: 0

The era of smart-everything has led to a surge in the need for semiconductor devices across a myriad of traditional and novel applications. These applications demand high performance yet energy-efficient compute over blazing-fast networks to service trillions of edge devices that are constantly consuming and generating large amounts of data. This surge has invigorated system architects to innov... » read more

Impact Of GAA Transistors At 3/2nm
By Brian Bailey - 16 Aug, 2021 - Comments: 2

The chip industry is poised for another change in transistor structure as gate-all-around (GAA) FETs replace finFETs at 3nm and below, creating a new set of challenges for design teams that will need to be fully understood and addressed. GAA FETs are considered an evolutionary step from finFETs, but the impact on design flows and tools is still expected to be significant. GAA FETs will offer... » read more

Designing Chips In A ‘Lawless’ Industry
By Ed Sperling - 02 Aug, 2021 - Comments: 2

The guideposts for designing chips are disappearing or becoming less relevant. While engineers today have many more options for customizing a design, they have little direction about what works best for specific applications or what the return on investment will be for those efforts. For chip architects, this is proving to be an embarrassment of riches. However, that design freedom comes wit... » read more

CEO Outlook: More Data, More Integration, Same Deadlines
By Ed Sperling - 24 Jun, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What ... » read more

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