tag: DFT

Streaming Scan Network
By Siemens EDA - 27 Jan, 2021 - Comments: 0

The increasing complexity in large System on Chip (SoC) designs present challenges to design-for-test (DFT). Hierarchical DFT alleviates some of those challenges, by itself, is no longer enough. Adding Tessent Streaming Scan Network (SSN) technology eliminates the difficult and costly trade-offs between test implementation effort and manufacturing test cost by decoupling core-level and chip-lev... » read more

DFT For SoCs Is Last, First, And Everywhere In Between
By Robert Ruiz - 12 Jan, 2021 - Comments: 0

Back in the dawn of time, IC test was the last task in the design flow. First, you designed the chip and then you wrote the functional test program to verify it performed as expected after manufacturing. Without much effort, some portion of the functional test program was often reused as the manufacturing test to determine that the silicon was defect-free. Fast forward to today and things ha... » read more

Digital Test Bulks Up – Or Down
By Bryon Moyer - 08 Dec, 2020 - Comments: 2

Large digital integrated circuits are becoming harder to test in a time- and cost-efficient manner. AI chips, in particular, have tiled architectures that are putting pressure on older testing strategies due to the volume of test vectors required. In some cases, these chips are so large that they exceed reticle size, requiring them to be stitched together. New testing efficiencies are needed... » read more

Week In Review: Design, Low Power
By Jesse Allen - 06 Nov, 2020 - Comments: 0

Tools Mentor unveiled Tessent Streaming Scan Network software for its Tessent TestKompress software. The new solution includes embedded infrastructure and automation that decouples core-level DFT requirements from the chip-level test delivery resources for a simplified bottom-up DFT flow. The bus-based scan data distribution architecture enables simultaneous testing of any number of cores and ... » read more

Scramble For The White Space
By Bryon Moyer - 13 Oct, 2020 - Comments: 0

Chipmakers are pushing to utilize more of the unused portion of a design for different functions, reducing margin in the rest of the chip to more clearly define that white space. White space typically is used to relieve back-end routing congestion before all of the silicon area is used up. But a significant amount of space still remain unused. That provides an opportunity for inserting monit... » read more

Using Critical Area To Boost Automotive IC Test Quality
By Ron Press - 03 Sep, 2020 - Comments: 0

To compete in the fast-growing market for automotive ICs, semiconductor companies need to address new challenges across the entire design flow. To meet the ISO 26262 goal of zero defective parts per million (DPPM), DFT engineers have embraced new test pattern types, including cell-aware, interconnect, and inter-cell bridge (cell neighborhood). But the traditional methods of choosing the types o... » read more

Critical Area-Based Test Pattern Optimization For High-Quality Test
By Mentor, a Siemens Business - 02 Sep, 2020 - Comments: 0

Among the challenges for DFT engineers is how to set a target metric for ATPG and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected doesn’t consider the likelihood of one fault occurring compared to another. Tessent developed total critical area ATPG technology that enables the sorting and ordering of patterns based on their likelihood... » read more

Test Is Becoming A Horizontal Process
By Ed Sperling - 10 Mar, 2020 - Comments: 3

Semiconductor test, once a discrete part of a well-orchestrated series of manufacturing steps, is looking more like a process that extends from the early concept stage in design to the end of life of whatever system that chip ultimately is used for. This has important ramifications for safety-critical markets in general, and the semiconductor industry in particular. Both worlds have been inc... » read more

AI Chip DFT Techniques For Aggressive Time-To-Market
By Mentor, a Siemens Business - 10 Mar, 2020 - Comments: 0

AI chips have aggressive time-to-market goals. Designers can shave significant time off of DFT and silicon bring up using the techniques described in this paper. Leading AI semiconductor companies have already had success with Tessent DFT tools. To read more, click here. » read more

Blog Review: Feb. 12
By Ed Sperling - 12 Feb, 2020 - Comments: 0

Complexity is growing by process node, by end application, and in each design. The latest crop of blogs points to just how many dependencies and uncertainties exist today, and what the entire supply chain is doing about them. Mentor's Shivani Joshi digs into various types of constraints in PCBs. Cadence's Neelabh Singh examines the complexities of verifying a lane adapter state machine in... » read more

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