tag: EUV

Extra! Extra! Read All About It!
By Marc David Levenson - 26 Feb, 2015 - Comments: 1

ASML announced that they are going into the pellicle business at 2:15pm on February 25 at the SPIE Advanced Lithography Symposium in San Jose. These are not your garden variety plastic membrane pellicles, mind you, but rather EUV pellicles made out of 50nm thick polysilicon film and stretched on frames that can be attached, removed and reattached on EUV masks. Dr. Carmen Zoldesi of ASML reveal... » read more

Manufacturing Bits: Feb. 24
By Mark LaPedus - 24 Feb, 2015 - Comments: 0

EUV progress report At the SPIE Advanced Lithography conference in San Jose, Calif., ASML Holding said that one customer, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), has exposed more than 1,000 wafers on an NXE:3300B EUV system in a single day. This is one step towards the insertion of EUV lithography in volume production. During a recent test run on the system, TSMC exposed 1,022 w... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 20 Feb, 2015 - Comments: 0

For years, chipmakers have attempted to build fabs in India. So far, however, India has failed to set up modern fabs and for good reason. There are issues in terms of obtaining dependable power and water for a fab in India, according to Will Strauss, president of Forward Concepts, who added that India also suffers from government bureaucracy. India is still trying. Last week, Cricket Semicon... » read more

5 Disruptive Mask Technologies
By Mark LaPedus - 19 Feb, 2015 - Comments: 0

Photomask complexity and costs are increasing at each node, thereby creating a number of challenges on several fronts. On one front, for example, traditional single-beam e-beam tools are struggling to keep up with mask complexity. As a result, the write times and costs continue to rise. Mask complexity also impacts the other parts of the tool flow, such as inspection, metrology and repair. I... » read more

How To Extend Litho Scaling
By Ann Mutschler - 19 Feb, 2015 - Comments: 0

IC mask [getkc id="80" comment="lithography"] today is sophisticated and complex. It's also a work in progress with a lot of unknowns as the industry struggles to increase productivity while reducing risk. The bulk of the work currently is focused on trying to figure out what would be a practical scheme for patterning lithography that could be used at 10nm and 7nm, said Gandharv Bhatara, Ca... » read more

One-On-One: Dave Hemker
By Mark LaPedus - 19 Feb, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Dave Hemker, senior vice president and chief technology officer at [getentity id="22820" comment="LAM Research"]. SE: On the technology front, the IC industry is undergoing some new and dramatic changes. What are some of those changes? Hemker: We focus on what we call the inflections.... » read more

First Look: 10nm
By Ed Sperling - 29 Jan, 2015 - Comments: 6

As the semiconductor industry begins grappling with mass production at 14/16nm process nodes, work is already underway at 10nm. Tools are qualified, IP is characterized, and the first test chips are being produced. It's still too early for production, of course—perhaps three years too early—but there is enough information being collected to draw at least some impressions about just how toug... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 23 Jan, 2015 - Comments: 0

The profile of a "tech geek" is typically a male. The label itself has transitioned from a negative to a positive connotation, according to new data from Crucial.com. In fact, almost half of women (45%) identified tech entrepreneurs as the most desirable potential spouse, compared to only 5% of women who would prefer a football player for a spouse. More than one in three women want a significan... » read more

One-On-One: Aaron Thean
By Mark LaPedus - 22 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec. SE: Chipmakers are ramping up the 16nm/14nm logic node, with 10nm and 7nm in R&D. What’s the current timeline for 10nm and 7nm? Thean: 10nm is on its way. We will see r... » read more

Fab Tool R&D And Ramen Noodles
By Mark LaPedus - 22 Jan, 2015 - Comments: 0

The semiconductor equipment and materials industry has always been a tough business. Over the years, vendors have been under pressure to develop new technologies for a shrinking but demanding customer base. And as a result, many vendors could not keep up, or elected to exit the business, causing a massive shakeout in the industry. It isn’t getting any easier, though. Today, tool and... » read more

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