tag: FD-SOI

Sorting Out Next-Gen Memory
By Mark LaPedus - 22 Sep, 2016 - Comments: 8

In the data center and related environments, high-end systems are struggling to keep pace with the growing demands in data processing. There are several bottlenecks in these systems, but one segment that continues to receive an inordinate amount of attention, if not part of the blame, is the memory and storage hierarchy. [getkc id="92" kc_name="SRAM"], the first tier of this hierarchy, is... » read more

7nm Market Heats Up
By Mark LaPedus - 15 Sep, 2016 - Comments: 2

The 7nm finFET market is heating up in the foundry business amid the ongoing push to develop chips at advanced nodes. Not long ago, TSMC announced plans to enter the 7nm finFET market. In addition, Intel and Samsung are also separately planning to enter the 7nm finFET race. Now, GlobalFoundries is formally announcing its 7nm finFET technology. Slated for 2018, GlobalFoundries’ 7nm fin... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 09 Sep, 2016 - Comments: 0

Chipmakers GlobalFoundries has rolled out its next-generation FD-SOI technology. The new 12nm FD-SOI process is called 12FDX. It is designed for a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. "Some applications require the unsurpassed performance of finFET transistors, but the vast majority of connected devices need high l... » read more

GlobalFoundries Rolls Out 12nm FD-SOI Process
By Jeff Dorsch - 08 Sep, 2016 - Comments: 0

GlobalFoundries uncorked its 12FDX platform, incorporating a 12nm fully-depleted silicon-on-insulator process technology. The foundry’s Fab 1 in Dresden, Germany, will support customer development with the 12nm process, with product tape-outs scheduled for the first six months of 2019. The 12FDX technology follows the company’s 22FDX platform involving a 22-nanometer process. The foundr... » read more

Focus Shifts To Architectures
By Ed Sperling - 08 Sep, 2016 - Comments: 1

Chipmakers increasingly are relying on architectural and micro-architectural changes as the best hope for improving power and performance across a spectrum of markets, process nodes and price points. While discussion about the death of [getkc id="74" comment="Moore's Law"] predates the 1-micron process node, there is no question that it is getting harder for even the largest chipmakers to st... » read more

Noise Killed My Chip
By Brian Bailey - 08 Sep, 2016 - Comments: 0

In the past, noise was considered an annoyance, especially for analog circuitry. But today chips are actually failing because insufficient analysis was performed. Noise types that used to be second-order effects are becoming primary factors that have to be considered. This is happening at the same time that noise margins are getting smaller, both in the amplitude and temporal dimensions. It ... » read more

What’s Important For IoT—Power, Performance Or Integration?
By Ed Sperling - 01 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down with Steve Hardin, director of product development for AT&T's IoT Solutions Group; Wayne Dai, CEO of VeriSilicon; John Koeter, vice president of the Solutions Group at [getentity id="22035" e_name="Synopsys"]; and Rajeev Rajan, vice president for IoT at [getentity id="22819" comment="GlobalFoundries"]. What follows are excerpts of that conversation. To vie... » read more

Stepping Back From Scaling
By Ed Sperling - 24 Aug, 2016 - Comments: 0

Architectures, packaging and software are becoming core areas for semiconductor research and development, setting the stage for a series of shifts that will impact a large swath of the semiconductor industry. While there is still demand from the largest chipmakers for increased density at the next process node, the underlying economics for foundries, equipment vendors and IP developers are f... » read more

How Small Will Transistors Go?
By Mark LaPedus - 18 Aug, 2016 - Comments: 1

By Mark LaPedus & Ed Sperling There is nearly universal agreement that Moore’s Law is slowing down. But whether it will truly end, or just become too expensive and less relevant—and what will supplant device scaling—are the subject of some far-reaching research and much discussion. Semiconductor Engineering sat down with each of the leaders of three top research houses—[getent... » read more

Reaching The Power Budget
By Ann Mutschler - 11 Aug, 2016 - Comments: 1

Everything related to power in chip design today is a big deal—and it’s just getting bigger. Meeting the power budget is becoming harder at each new node, but it's also becoming difficult in a number of new application areas at existing nodes. That's a big problem because [getkc id="108" kc_name="power"] is now considered a competitive advantage in many markets. It's also one of the most... » read more

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