Bridging Hardware And Software

By Ann Mutschler - 22 Dec, 2015 - Comments: 0

Since the advent of embedded systems there has been a struggle between hardware engineers trying to understand the mindset of their software counterparts, and vice versa. That struggle is alive and well today—and it's costing everyone money. This divide is rife with passion, territoriality and misunderstanding. It has delayed tapeouts, created errors and inefficiencies that take time and e... » read more

Tech Talk: Configurable Logic

By Ed Sperling - 08 Oct, 2015 - Comments: 0

Cliff Lloyd, business development director at NXP Semiconductors, talks about designing in one part for many functions to reduce power consumption and cost. [youtube vid=ut5kCm0kNwE] » read more

SoC Verification Made Easy With Aldec HES-DVM

By Aldec - 23 Sep, 2015 - Comments: 0

As designs grow larger, the time spent verifying a project is growing longer as well. As a solution, some companies are trying to ‘shift-left’ their schedules. Verification via software simulators is not fast enough for large System-on-Chip (SoC) design projects, therefore one option is to use an FPGA emulator to speed up the design process. But what happens when a bug occurs? This document... » read more

Blog Review: Sept. 9

By Ed Sperling - 09 Sep, 2015 - Comments: 0

Doulos' John Aynsley explains in a guest blog for Aldec why FPGA designers need to know SystemVerilog and UVM. Might be time to increase the coffee budget. Speaking of verification, Cadence's Frank Schirrmeister notes that his company is joining forces with Mentor Graphics and Breker for a contribution to the Accellera Portable Stimulus Working Group. This is potentially a big deal in veri... » read more

Rethinking Differentiation

By Ed Sperling - 28 Aug, 2015 - Comments: 0

Differentiation is becoming more difficult, more time-consuming, and in some cases much more expensive for chipmakers. The traditional metrics of faster performance, lower power and less area/cost, which are leftovers from the PC era, no longer are a guarantee of success despite the fact that they are still baseline metrics for many designs. Even new metrics such as ecosystem completeness, w... » read more

Top 15 Integrating Points In The Continuum Of Verification Engines

By Frank Schirrmeister - 30 Jul, 2015 - Comments: 0

The integration game between the different verification engines, dynamic and static, is in full swing. Jim Hogan talked about the dynamic engines that he dubbed “COVE”, and I recently pointed out a very specific adoption of COVE in my review of some customer examples at DAC 2015 in “Use Model Versatility Is Key for Emulation Returns on Investment”. Here are my top 15 integrating poin... » read more

Accelerate SoC Simulation Time Of Newer Generation FPGAs

By Aldec - 29 Jul, 2015 - Comments: 0

Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform. To read more, click here. » read more

The Week In Review: Manufacturing

By Mark LaPedus - 05 Jun, 2015 - Comments: 1

In what was called a defensive measure by some, Intel has announced a definitive agreement to acquire Altera for $54 per share in an all-cash transaction valued at approximately $16.7 billion. Here’s what one analyst said about the deal. “We continue to believe Intel’s pursuit of Altera–at a significant premium–was based on a defensive position, rather than the purely accretive str... » read more

Blog Review: May 27

By Jesse Allen - 27 May, 2015 - Comments: 0

With the launch of UNICEF and ARM's 'Wearables for Good' design challenge, David Maidment digs into the program's details and how unobtrusive wearables and sensor technology benefits not only consumers in affluent countries, but could improve conditions for those in the developing world as well. From an ultracompact beamsplitter that could boost processing power for supercomputers within the... » read more

Ecosystem Changes

By Ed Sperling - 07 Apr, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss changes in the semiconductor ecosystem with Kelvin Low, senior director of foundry marketing at [getentity id="22865" e_name="Samsung Semiconductor"]; John Costello, vice president of product planning at [getentity id="22849" e_name="Altera"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"], and Michiel Ligthart, p... » read more

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Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

tag: FPGA