ML-based Routing Congestion And Delay Estimation In Vivado ML Edition


The FPGA physical design flow offers a compelling opportunity for Machine Learning for CAD (MLCAD) for the following reasons: • An ML solution can be applied wholesale to a device family. • There is a vast data farm that can be harvested from device models and design data from broad applications. • There is a single streamlined design flow that an be instrumented, annotated, and quer... » read more

Hierarchical Verification for EC-FPGA Flow


This document describes the methodology to apply EC-FPGA verification using hierarchical netlists. This approach is recommended in case the verification of the overall design has issues with convergence. The document contains a step-by-step description of different methods while providing reasoning for the soundness of each approach. It is assumed for this document that the reader is familiar w... » read more

Rising Fortunes For ICs In Health Care


Semiconductors are increasingly finding their way into a variety of medical devices, after years of slow growth and largely consumer electronics types of applications. Nearly every major chipmaker has a toehold in health care these days, and many are starting to look beyond wearable such as the Apple Watch to devices that can be relied on for accuracy and reliability. Unlike in the past, the... » read more

Adaptive Computing In Robotics


Traditional software development in robotics is about programming functionality in the CPU of a given robot with a pre-defined architecture and constraints. With adaptive computing, instead, building a robotic behavior is about programming an architecture. By leveraging adaptive computing, roboticists can adapt one or more of the properties of its computing systems (e.g., its determinism, power... » read more

Security Risks Grow With 5G


5G mobile phones can download a movie in seconds rather than minutes, but whether that can be done securely remains to be seen. What is clear from technology providers, though, is they are taking security very seriously with this new wireless technology. More data is in motion, and the value of that data is growing as users rely on mobile devices for everything from banking to automotive saf... » read more

Building Complex Chips That Last Longer


Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Integrate FPGAs For A Customizable MCU


MCUs come in a broad range of flavors, meaning you can pick the best one for the application with the right performance, feature set, peripherals, memory, and software programmability. So, then, why do many systems also use FPGAs next to the MCUs? Usually, it’s because there’s not a “perfect” MCU for their application. MCUs by definition are built to be generic for a wide variety of app... » read more

Solution Efficiencies For Dynamic Function eXchange Using Abstract Shells


Dynamic Function eXchange (DFX) enables great flexibility within Xilinx® silicon, empowering you to load applications on demand, deliver updates to deployed systems, and reduce power consumption. Platform designs allow for collaboration between groups, where one group can focus on infrastructure and another on hardware acceleration. However, DFX has fundamental flow requirements that lead to l... » read more

Developing A Real-Time SDR System


As telecommunication technologies evolve there is an on-going drive for the development of high-performance systems for radio communications. Part of that evolution involves implementing components in software functions that had traditionally been implemented in hardware. Software-defined radio (SDR) is a prime example. Significant amounts of signal processing have been handed over to the ge... » read more

Automated Conversion Of Xilinx Vivado Projects To ALINT-PRO


Aldec's ALINT-PRO design verification solution performs static RTL and design constraints code analysis to uncover critical design issues early in the design cycle. The product helps FPGA developers rise to the challenge of designing large FPGA designs and multiprocessor system on chip devices that include high-capacity and high-performance FPGA hardware. The solution supports running rule c... » read more

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