tag: IP

Understanding NI CompactRIO Scan Mode
By NI - 07 May, 2018 - Comments: 0

The LabVIEW Real-Time Module 8.6 introduced powerful new features for programming CompactRIO hardware that reduce development time and complexity as well as provide tools for monitoring and maintaining CompactRIO applications. This functionality is powered by two technologies in LabVIEW, the NI Scan Engine and the RIO Scan Interface. The NI Scan Engine is a new component of LabVIEW Real-Time th... » read more

The Week In Review: Design
By Jesse Allen - 04 May, 2018 - Comments: 0

M&A ANSYS finalized its acquisition of OPTIS. Founded in 1989, OPTIS provided software for scientific simulation of light, human vision and physics-based visualization. The acquisition boosts the company's automotive simulation portfolio with radar, lidar and camera simulation. Terms were not disclosed. IP Arm debuted the Cortex-M35P processor. Aimed at IoT applications, the IP combine... » read more

EDA In The Cloud (Part 2)
By Brian Bailey - 02 May, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the migration of EDA tools into the Cloud with Arvind Vel, director of product management at ANSYS; Michal Siwinski, vice president of product management at Cadence; Richard Paw, product marketing manager at DellEMC, Gordon Allan, product manager at Mentor, a Siemens Business; Doug Letcher, president and CEO of Metrics, Tom Anderson, technical marke... » read more

Partitioning Becomes More Difficult
By Ann Mutschler - 30 Apr, 2018 - Comments: 0

The divide-and-conquer approach that has been the backbone of verification for decades is becoming more difficult at advanced nodes. There are more interactions from different blocks and features, more power domains, more physical effects to track, and far more complex design rules to follow. This helps explain why the number of tools required on each design—simulation, prototyping, em... » read more

Hidden Costs Of Shifting Left
By Brian Bailey - 26 Apr, 2018 - Comments: 0

The term "Shift Left" has been used increasingly within the semiconductor development flow to indicate tasks that were once performed sequentially must now be done concurrently. This is usually due to a tightening of dependences between tasks. One such example being talked about today is the need to perform hardware/software integration much earlier in the flow, rather than leaving it as a sequ... » read more

IP Issues At 10/7nm
By Ranjit Adhikary - 23 Apr, 2018 - Comments: 0

For years chip makers have been demanding more options to assist them in getting silicon to market faster. As of 2018, there are now so many possibilities for chip makers that engineering teams of all types are having trouble wading through all the possibilities. To make matters worse, many of today’s choices now come with unexpected and often unwanted caveats. At the most advanced nodes... » read more

Tech Talk: Analog Simplified
By Ed Sperling - 16 Apr, 2018 - Comments: 0

Benjamin Prautsch, Fraunhofer EAS' group manager for advanced mixed-signal automation, talks about how to simplify and speed up analog IP development, its role in IoT and IIoT/Industry 4.0, and why this is becoming so important for advanced packaging and advanced process nodes. https://youtu.be/6ISL1A7Wy_I » read more

What Happened To UPF?
By Brian Bailey - 16 Apr, 2018 - Comments: 1

Two years ago there was a lot of excitement, both within the industry and the standards communities, about rapid advancements that were being made around low-power design, languages and methodologies. Since then, everything has gone quiet. What happened? At the time, it was reported that the [gettech id="31043" comment="IEEE 1801"] committee was the largest active committee within the IEEE. ... » read more

Get Ready For Integrated Silicon Photonics
By Brian Bailey - 12 Apr, 2018 - Comments: 1

Long-haul communications and data centers are huge buyers of photonics components, and that is leading to rapid advances in the technology and opening new markets and opportunities. The industry has to adapt to meet the demands being placed on it and solve the bottlenecks in the design, development and fabrication of integrated silicon photonics. "Look at the networking bandwidth used across... » read more

Tiling Is Critical For eFPGA Users: ArrayLinx Delivers
By Flex Logix - 04 Apr, 2018 - Comments: 0

FPGA chips come in multiple sizes — modular blocks of programmable logic, DSP MACs and RAM are intermixed in different sizes and ratios then stitched together with top-level interconnect, clocking, etc and surrounded by a ring of I/Os like GPIO, SerDes, USB, etc. There is extensive engineering and top-level physical design for each distinct FPGA array and chip. eFPGA is different: Custome... » read more

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