Machine Learning Showing Up As Silicon IP

By Bryon Moyer - 03 Mar, 2022 - Comments: 0

New machine-learning (ML) architectures continue to appear. Up to now, each new offering has been implemented in a chip for sale, to be placed alongside host processors, memory, and other chips on an accelerator board. But over time, more of this technology could be sold as IP that can be integrated into a system-on-chip (SoC). That trend is evident at recent conferences, where an increasing... » read more

Preparing For Test Early In The Design Flow

By Ann Mutschler - 02 Mar, 2022 - Comments: 0

Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and increasingly complex chip architectures. In the past, products were designed from a functional perspective, and designers were not concerned about what the physical implementation of the product ... » read more

Design Challenges Increasing For Mixed-Die Packages

By Ann Mutschler - 09 Feb, 2022 - Comments: 0

The entire semiconductor ecosystem is starting to tackle a long list of technology and business changes that will be needed to continue scaling beyond Moore's Law, making heterogeneous combinations of die easier, cheaper, and more predictable. There are a number of benefits to mixing die and putting them together in a modular way. From a design standpoint, this approach provides access to th... » read more

The Risk Of Losing Track Of Your IP

By Ed Sperling - 12 Jan, 2022 - Comments: 0

What happens when you misuse IP, intentionally or otherwise? Pedro Pires, applications engineer at Cliosoft, talks about the challenges of keeping track of IP across multiple chip design projects, which can grow to include dozens of third-party IP blocks, last for long periods of years, and span multiple continents. » read more

Quantifiable Assurance: From IPs to Platforms

By Technical Paper Link - 10 Jan, 2022 - Comments: 0

Abstract: "Hardware vulnerabilities are generally considered more difficult to fix than software ones because of their persistent nature after fabrication. Thus, it is crucial to assess the security and fix the potential vulnerabilities in the earlier design phases, such as Register Transfer Level (RTL), gate-level or physical layout. The focus of the existing security assessment techniques i... » read more

Challenges With Stacking Memory On Logic

By Ed Sperling - 22 Dec, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

Flexible USB4-Based Interface IP Solution For AI At The Edge

By Synopsys - 21 Dec, 2021 - Comments: 0

Consumers have become accustomed to smart devices that are powered by advances in artificial intelligence (AI). To expand the devices’ total addressable market, innovative device designers build edge AI accelerators and edge AI SoCs that support multiple use cases and integration options. This white paper describes a flexible USB4-based IP solution for edge AI accelerators and SoCs. The IP so... » read more

Why It’s So Difficult — And Costly — To Secure Chips

By Ed Sperling - 02 Dec, 2021 - Comments: 0

Rising concerns about the security of chips used in everything from cars to data centers are driving up the cost and complexity of electronic systems in a variety of ways, some obvious and others less so. Until very recently, semiconductor security was viewed more as a theoretical threat than a real one. Governments certainly worried about adversaries taking control of secure systems through... » read more

Three Key Aspects Of IP Quality

By Tom Anderson - 02 Dec, 2021 - Comments: 0

It’s no secret that today’s huge system-on-chip (SoC) projects require massive amounts of design reuse. No team, no matter how talented, can design a billion or more gates from scratch. They use extensive borrowing of RTL code from previous and related projects, plus hundreds of thousands of instantiated IP blocks from internal libraries, open-source repositories, development partners, and ... » read more

Effectively Addressing The Challenge Of Securing Connected And Autonomous Vehicles

By Siemens EDA - 01 Dec, 2021 - Comments: 0

Vehicles are becoming the most sophisticated connected objects in the ‘Internet of Things’. As vehicles integrate functionality that will enable a fully autonomous future, the attack surface grows substantially. Combined with remote connectivity at multiple points, the clock is ticking in a race to improve cybersecurity in all types of vehicles to ensure that all stakeholders, but particula... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: IP