tag: IP

New Math: 1+1=1?
By Ed Sperling - 07 May, 2010 - Comments: 0

From the standpoint of place and route, synthesis, and even some pieces of the hardware verification, the cost of chips even at advanced nodes hasn’t budged. It’s now possible to create a chip at 28nm with roughly the same budget as a 40nm chip, and inside many companies that’s what the hardware engineering manager sees. Look across the entire SoC design chain, however, and the picture... » read more

Integrated IP Goes Vertical
By Ed Sperling - 25 Mar, 2010 - Comments: 0

By Ed Sperling The consolidation of intellectual property from small developers to large players with integrated IP blocks is accelerating. Large IP companies are now developing integrated suites that are pre-tested for specific vertical markets, and new companies are sprouting up to make it easier to put even broader collections of IP together in meaningful ways. It’s difficult to te... » read more

Meeting The Challenge Of Verification In Low-Power Designs
By Ed Sperling - 12 Nov, 2009 - Comments: 0

By Cheryl Ajluni Over the years, new techniques, technologies and design tools have been brought to market with the explicit intent of simplifying design verification. Despite these efforts verification still manages to consume a huge chunk of the time spent during design. By some accounts that number tops 70%. The problem is that verification is hard, and it certainly doesn’t get an easi... » read more

Relocating Intelligence
By Ed Sperling - 23 Oct, 2009 - Comments: 0

For the past couple of decades, intelligence in a system was largely a function of the logic in a processor. That may change, given some of the disparate discussions now under way across the electronics industry. Putting all the intelligence in one place can make the design process more efficient, but it doesn’t necessarily make the system more efficient, either from a performance or pow... » read more

Tires That Talk
By Ed Sperling - 14 Sep, 2009 - Comments: 0

[youtube vid=JHxu-FWYxlw] » read more

Experts At The Table: Building A Better Mousetrap
By Ed Sperling - 28 Aug, 2009 - Comments: 0

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at ... » read more

Exclusive Research: What’s Happening With Third-Party IP
By Ed Sperling - 27 Mar, 2009 - Comments: 0

Analog and mixed signal IP began closing the gap with digital core IP in design explorations in the first two months of this year, a clear sign that multicore systems on chip have emerged as the dominant semiconductor model and that the architecture requires both types of IP. While it’s too early to tell this year what effect that will have on overall design activity—the economy is the rea... » read more

Verifying Low-Power IP And Designs
By Ed Sperling - 13 Mar, 2009 - Comments: 0

By Ed Sperling Verification has always been the time-consuming part of designs. Even at 120nm and above, where power wasn’t much of an issue, verification accounted for an estimated 70 percent of the non-recurring engineering expense in a chip. Since then, the tools to automate design have become more effective, but the complexity of designs has grown by leaps and bounds beyond those tools.... » read more

Next Steps In Verification IP
By Ann Mutschler - 19 Feb, 2009 - Comments: 0

By Ann Steffora Mutschler With the cost of failure at an astronomical high, the last thing chip designers want to worry about is the physical IP they will use to build their SoC. In addition to less willingness on the customer’s behalf to take risks, complexity and economics have driven the need for more off-the-shelf IP and a corresponding rise in interest in verification IP. Compoundi... » read more

Making A Multicore System Work
By Ed Sperling - 29 Jan, 2009 - Comments: 0

If you think designing a single-core system is hard, designing multicore systems is multiple times harder. Connecting all the pieces together and making them work properly, if not together, is one of the hardest tasks design engineers and architects will ever face. System-Level Design tracked down some of the experts in this field and sat them down around a table to discuss what’s going... » read more

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