tag: lithography

Executive Insight: Aart de Geus
By Ed Sperling - 20 Jul, 2016 - Comments: 0

Aart de Geus, chairman and co-CEO of Synopsys, sat down with Semiconductor Engineering to discuss Moore's Law, the IoT, inflection points and how chip design will evolve in coming years. SE: We are in the middle of possibly one of the biggest transition points we’ve ever seen in this industry. How do you envision things shaking out? De Geus: There is no question that there is an enormou... » read more

Introduction To Multi-Patterning
By Mentor, a Siemens Business - 20 Jul, 2016 - Comments: 0

Multi-patterning enables accurate lithographic resolution at today's most advanced nodes. Learn about the basics of this technology, and how it impacts your IC design and verification tasks and responsibilities. To read more, click here. » read more

IMEC Partner Technical Week Review
By Aurélie Juncker - 23 Jun, 2016 - Comments: 0

In March 2016, Coventor was invited to the biannual Partner Technical Week (PTW) at IMEC in Leuven, Belgium. IMEC, a world-leading research group in nanotechnology, organizes their Partner Technical Week every six months to present scientific results to their partners. During this week, a number of specialists from IMEC's many partner companies also discuss their progress in areas related to IM... » read more

Executive Insight: Aki Fujimura
By Mark LaPedus - 23 Jun, 2016 - Comments: 1

Aki Fujimura, chief executive of D2S, sat down with Semiconductor Engineering to look at the key issues in lithography and photomasks, as well as the changes taking place in the IC industry. What follows are excerpts of that conversation. SE: The semiconductor market is changing on several fronts. On one front, there is a wave of consolidation in the industry. And then there is a slowdown in... » read more

Manufacturing Bits: June 21
By Mark LaPedus - 21 Jun, 2016 - Comments: 0

Atomic sculpting Oak Ridge National Laboratory has combined a scanning transmission electron microscope (STEM) with new electronic controls. This tool enables the construction, or the atomic sculpting, of 3D-like feature sizes down to 1nm and 2nm. To achieve these dimensions, the STEM is controlled with a special set of programmable electronics. This, in turn, enables the STEM to tunnel in... » read more

One-On-One: Dave Hemker
By Ed Sperling - 19 May, 2016 - Comments: 0

Dave Hemker, CTO at [getentity id="22820" comment="Lam Research"], sat down with Semiconductor Engineering to look at some of the key issues on the process and manufacturing side, and some of the key developments that will reshape the semiconductor industry in the future. What follows are excerpts of that conversation. SE: One of the big discussion topics these days is [getkc id="208" commen... » read more

7nm Fab Challenges
By Mark LaPedus - 21 Apr, 2016 - Comments: 3

Leading-edge foundry vendors have made the challenging transition from traditional planar processes into the finFET transistor era. The first [getkc id="185" kc_name="finFETs"] were based on the 22nm node, and now the industry is ramping up 16nm/14nm technologies. Going forward, the question is how far the finFET can be scaled. In fact, 10nm finFETs from Samsung are expected to ramp by ye... » read more

Inside Process Technology
By Mark LaPedus - 21 Apr, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss the foundry business, memory, process technology, lithography and other topics with David Fried, chief technology officer at [getentity id="22210" e_name="Coventor"], a supplier of predictive modeling tools. What follows are excerpts of that conversation. SE: Chipmakers are ramping up 16nm/14nm finFETs today, with 10nm and 7nm finFETs just around... » read more

Foundation IP For 7nm FinFETs: Design And Implementation
By Synopsys - 13 Apr, 2016 - Comments: 0

Learn about the challenges of IP design and implementation for 7nm FinFETs. Along with the performance and area benefits that the node brings, designers must understand the significant technical challenges stemming from increasing variability associated with tighter pitches and more complex lithography steps. Design for variability and reliability considerations will require comprehensive model... » read more

Where Is Next-Gen Lithography?
By Mark LaPedus - 11 Apr, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Greg McIntyre, director of the Advanced Patterning Department at Imec; Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries; Uday Mitra, vice president and head of strategy and marketing for the Etch Business Unit and Patterning Module at Applied Materials; Naoya Haya... » read more

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