Targeting Redundancy In ICs


Technology developed for one purpose is often applicable to other areas, but organizational silos can get in the way of capitalizing on it until there is a clear cost advantage. Consider memory. All memories are fabricated with spare rows and columns that are swapped in when a device fails manufacturing test. "This is a common method to increase the yield of a device, based on how much memor... » read more

How To Improve Software? Start With The Hardware


By Travis Walton and Udi Maor Physicist Art Rosenfeld was working late at Lawrence Berkeley National Lab one night in 1973 when he noticed it. Despite an ongoing energy crisis, his colleagues routinely left their lights on after they left. Waste was one of the largest consumers of power in the state, he soon discovered: pilot lights consumed 10% of gas in homes. Switching from physics to ... » read more

Accelerating AI/ML Inferencing With GDDR6 DRAM


The origins of graphics double data rate (GDDR) memory can be traced to the rise of 3D gaming on PCs and consoles. The first graphics processing units (GPU) packed single data rate (SDR) and double data rate (DDR) DRAM – the same solution used for CPU main memory. As gaming evolved, the demand for higher frame rates at ever higher resolutions drove the need for a graphics-workload specific me... » read more

Is There a Practical Test For Rowhammer Vulnerability?


Rowhammer is proving to be a difficult DRAM issue to fix. While efforts continue to mitigate or eliminate the effect, no solid solution has yet made it to volume production. In addition, more aggressive process nodes are expected to exacerbate the problem. In the absence of a fix, then, testing may be one way to give DRAM manufacturers and users some way to segregate devices that are more su... » read more

11 Ways To Reduce AI Energy Consumption


As the machine-learning industry evolves, the focus has expanded from merely solving the problem to solving the problem better. “Better” often has meant accuracy or speed, but as data-center energy budgets explode and machine learning moves to the edge, energy consumption has taken its place alongside accuracy and speed as a critical issue. There are a number of approaches to neural netw... » read more

Steep Spike For Chip Complexity And Unknowns


Cramming more and different kinds of processors and memories onto a die or into a package is causing the number of unknowns and the complexity of those designs to skyrocket. There are good reasons for combining all of these different devices into an SoC or advanced package. They increase functionality and can offer big improvements in performance and power that are no longer available just b... » read more

Shifting Auto Architectures


Domain controllers and gateways are being replaced by central processing modules and zonal gateways to handle all of the data traffic in a vehicle. Ron DiGiuseppe, automotive IP segment manager at Synopsys, talks with Semiconductor Engineering about how automotive applications are changing, what that means for engineering teams, and how they will shift as AI is increasingly deployed. » read more

More Data Drives Focus On IC Energy Efficiency


Computing workloads are becoming increasingly interdependent, raising the complexity level for chip architects as they work out exactly where that computing should be done and how to optimize it for shrinking energy margins. At a fundamental level, there is now more data to compute and more urgency in getting results. This situation has forced a rethinking of how much data should be moved, w... » read more

Understanding Write Combining On Arm


Write Combining (WC) is a specialized memory type defined by the x86-64 architecture that is used for gathering multiple stores into burst transactions over the system bus. WC is commonly used on x86-64 platforms for interaction with I/O and other peripheral devices. In this whitepaper we provide an overview of the Arm architecture memory types that provide WC-like capabilities. In addition, t... » read more

Computing Where Data Resides


Computational storage is starting to gain traction as system architects come to grips with the rising performance, energy and latency impacts of moving large amounts of data between processors and hierarchical memory and storage. According to IDC, the global datasphere will grow from 45 zettabytes in 2019 to 175 by 2025. But that data is essentially useless unless it is analyzed or some amou... » read more

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