tag: Mentor Graphics

Blog Review: May 28
By Ed Sperling - 28 May, 2014 - Comments: 0

Ansys’ Robert Harwood examines the crossover between drones and 3D printing—particularly ones that can make repairs in inaccessible or hazardous areas. That could make both of them more popular. Mentor’s Mathew Clark puts a new spin on the term “gumming up the works.” Poor little things. Cadence’s Brian Fuller drills into Google’s Project Ara, the magnetic LEGO architecture ... » read more

Test Challenges Grow
By Mark LaPedus - 27 May, 2014 - Comments: 3

Semiconductor Engineering sat down to discuss current and future test challenges with Dave Armstrong, director of business development at Advantest; Steve Pateras, product marketing director for Silicon Test Solutions at Mentor Graphics; Robert Ruiz, senior product marketing manager at Synopsys; Mike Slessor, president of FormFactor; and Dan Glotter, chief executive of Optimal+. SE: In our ... » read more

The Week In Review: Design
By Ed Sperling - 23 May, 2014 - Comments: 0

M&A Mentor Graphics acquired Nimbic, which makes simulation software for power and signal integrity and electromagnetic interference. No purchase price was given. Synopsys’ Coverity subsidiary acquired Kalistick, which makes cloud-based software solutions to boost test efficiency. Terms of the deal were not provided. Tools and IP Sonics introduced a new development environment for... » read more

EDA Economics Changing
By Ed Sperling - 22 May, 2014 - Comments: 0

From most perspectives, there has never been a better time to be in the EDA business. Automation tools are in demand as complexity rises, and new companies jumping into the semiconductor business are starting out with commercially available tools rather than developing their own—and taking years, sometimes even decades, to replace them. EDA’s slice of the semiconductor market consistent... » read more

The Assertion Conundrum
By Ann Mutschler - 22 May, 2014 - Comments: 2

It is well documented and widely agreed that assertions can provide a tremendous benefit to design and verification teams by reducing and even eliminating debug – but their use is still not ubiquitous. Part of the reason is that assertions cannot be picked up casually, noted David Larson, director of verification at [getentity id="22150" e_name="Synapse Design"]. “This is because asserti... » read more

New Uses For Emulation
By Ed Sperling - 22 May, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss the changing emulation landscape with Jim Kenney, director of marketing for emulation at Mentor Graphics; Tom Borgstrom, director of the verification group at Synopsys; Frank Schirrmeister, group director of product marketing for the System Development Suite at Cadence; Gary Smith, chief analyst at Gary Smith EDA; and Lauro Rizzatti, a verification ... » read more

When And Where To Use Virtual Prototypes
By Ann Mutschler - 22 May, 2014 - Comments: 0

Just because something is technically possible doesn’t always mean it should be done. This definitely holds true currently when it comes to virtual prototypes, which have gotten a lot of attention for their potential in the SoC design process—especially for concurrent software development. While no one is pointing fingers, there are situations in which design teams have thrown themselves... » read more

Executive Insight: Adnan Hamid
By Brian Bailey - 22 May, 2014 - Comments: 1

Semiconductor Engineering sat down with Adnan Hamid, founder and CEO of Breker Verification Systems. Breker was founded in 2003 and has been concentrating on the creation of verification methodologies for multiprocessor SoCs using graph-based entry methods – something that became a hot topic at DVCon 2014 after Mentor Graphics decided to donate its format to Accellera for standardization. ... » read more

The Circle Of Test And EDA Is Complete
By Brian Bailey - 22 May, 2014 - Comments: 1

For those of you who were around and involved with EDA back in the early ’80s, you may remember that chip design was not the focus. It was the board that received most of the attention. Chips were small and did not require much in the way of functional verification. [getkc id="29" kc_name="Synthesis"] had not been invented and so gate-level design was where everything happened, and much of th... » read more

FinFET And Multi-Patterning Aware Place And Route Implementation
By Mentor, a Siemens Business - 21 May, 2014 - Comments: 0

The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Olympus-SoC place and route system handles them. To view this white paper, click here. » read more

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