tag: Mentor Graphics

Reaching For ROI
By Ann Mutschler - 17 Feb, 2016 - Comments: 0

The simplest way to assess power and performance ROI of a chip design is to ask if the chip works and whether it meets the design specifications. But chips can be used in very different ways, and a single chip may have a number of operational modes, so that formula isn't so clear anymore. "Preventing failures is the No. 1 priority when it comes to ROI," said Aveek Sarkar, vice president of p... » read more

Blog Review: Feb. 17
By Jesse Allen - 17 Feb, 2016 - Comments: 0

While there have been successes for 3D-IC, the technology has stalled trying to move into the mainstream market, says Mentor's Michael White. So what has kept it from crossing the chasm? Synopsys' Robert Vamosi takes a look at the US government's latest efforts towards improving cybersecurity. Cadence's Paul McLellan discusses the importance of software-driven hardware verification and th... » read more

The Week In Review: Design/IoT
By Jesse Allen - 12 Feb, 2016 - Comments: 0

Imagination's Sir Hossein Yassaie stepped down as Chief Executive, and Andrew Heath, one of the non-executive directors, has been appointed Interim Chief Executive. As part of a major restructuring, the company will also sell Pure, its consumer electronics business. Mentor Graphics' Embedded Linux platform has been updated to Yocto 2.0 and expanded to include new security enhancements and ad... » read more

Will 3D-IC Work?
By Ed Sperling - 11 Feb, 2016 - Comments: 3

Advanced packaging is becoming real on every level, from fan-outs to advanced fan-outs, 2.5D, and 3D-ICs for memory. But just how far 3D and monolithic 3D will go isn't clear at this point. The reason is almost entirely due to heat. In a speech at SEMI's Integrated Strategy Symposium in January, Babek Sabi, Intel corporate VP and director of assembly and test technology development, warned t... » read more

Debug Becomes A Bigger Problem
By Brian Bailey - 11 Feb, 2016 - Comments: 3

The EDA industry has invested enormous amounts of time and energy on the verification process, including new languages, new tools, new class libraries, new methodologies. But the one part of the cycle that defines that type of automation is debug. Development teams are spending half of their time in the debug process and the problem is growing. Part of the reason is that design and debug are... » read more

Thermal Damage To Chips Widens
By Ed Sperling - 11 Feb, 2016 - Comments: 1

Heat is becoming a much bigger problem for semiconductor and system design, fueled by higher density and the increasing use of complex chips in markets such as automotive, where reliability is measured in decade-long increments. In the past, heat typically was handled by mechanical engineers, who figured out where to put heat sinks, fans, or holes to funnel heat out of a chassis. But as more... » read more

Automating Coverage And Analysis Of Low Power Designs
By Ellie Burns - 11 Feb, 2016 - Comments: 0

There are some exciting new things in the just released IEEE1801-2015 (aka UPF 3.0), some of which have significant benefits for coverage of low power designs, which is what we’ll be looking at in this blog. One of these is improved semantics for the add power state command, introduced in IEEE1801-2009 (aka UPF 2.0). These clarifications to the add power state command allow you to clearly ... » read more

Powerful New Standard
By Brian Bailey - 11 Feb, 2016 - Comments: 0

In December the IEEE released the latest version of the 1801 specification, entitled the IEEE standard for design and verification of low-power integrated circuits. Most people know it as UPF, or the Unified Power Format. That was the name the first version of it held while being developed within Accellera. The standard provides a way to specify the power intent associated with a design, enabli... » read more

Next-Generation RTL Floorplanning
By Mentor, a Siemens Business - 10 Feb, 2016 - Comments: 0

Mentor’s physical RTL synthesis tools, including RealTime Designer and next-generation products, have the unique technology to pull placement ahead of synthesis and address the need for RTL floorplanning. Mentor’s physical RTL synthesis tools offer higher capacity, faster runtimes, optimal QoR, and physical awareness during RTL synthesis by optimizing at a higher level of abstraction and u... » read more

Blog Review: Feb. 10
By Jesse Allen - 10 Feb, 2016 - Comments: 0

You could be flying on a hybrid plane that uses hydrogen fuel cells in the future, and might even be able to hear the loudspeaker announcements while waiting for the flight, in this week's top tech picks from Ansys' Justin Nescott. Plus, smart soccer balls. Thermal is the new power, argues Cadence's Paul McLellan, and when it comes to SoCs treating thermal analysis as an afterthought is no l... » read more

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