tag: Mentor Graphics

FinFET Rollout Slower Than Expected
By Mark LaPedus - 16 Apr, 2015 - Comments: 1

The foundry business is heating up as some new and large players are entering the 16nm/14nm [getkc id="185" kc_name="finFET"] market. But foundry customers are taking longer than expected to migrate to finFETs amid some technical and cost issues. On the foundry front, [getentity id="22846" comment="Intel"] has been the sole player in finFETs for some time. But now, [getentity id="22865" ... » read more

Faster Time To Root Cause With Diagnosis-Driven Yield Analysis
By Mentor, a Siemens Business - 16 Apr, 2015 - Comments: 0

ICs developed at advanced technology nodes of 65 nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues. Without improved yield analysis methods, time-to-volume is delayed... » read more

Blog Review: April 15
By Jesse Allen - 15 Apr, 2015 - Comments: 0

How much memory do you need to look 13 billion years in the past? Rambus' Aharon Etengoff ponders the Square Kilometre Array's massive number of radio telescopes and what it means for computing. NXP's Martin Schoessler argues that for smart cities to work for their citizens, both technology companies and government entities will need a new mind-set. Reinventing the wheel is a good thing i... » read more

EDA Sets New Record
By Ed Sperling - 13 Apr, 2015 - Comments: 0

EDA revenue grew 11.9% in Q4 2014 to $2.1 billion, a new record for the industry, propelled by strong growth in both IP and physical design. On a sequential basis, that represented a 15.1% increase, while on a year-over-year basis it was 11.9%. The four-quarter moving average, which takes into account quarterly aberrations, showed a 7.3% increase. "The semiconductor industry had a strong ... » read more

Week 44: IoT impossible Without EDA
By Anne Cirkel - 10 Apr, 2015 - Comments: 1

Hype and timing aside, the IoT is likely to be the Internet’s next wave. Like all new waves, IoT probably won’t bear much resemblance to the descriptions of today’s prognosticators, though will lean heavily on earlier work and innovation – including by the EDA technologies that remain the core of DAC and our multibillion dollar industry, and the prime enabler of electronic design at lar... » read more

The Week In Review: Design/IoT
By Jesse Allen - 10 Apr, 2015 - Comments: 0

Certifications TSMC certified a number of tools for its current 10nm FinFET design rules and SPICE models and 16nm FinFET Plus (16FF+) V1.0 process, including: Ansys' power integrity and electromigration tools; Cadence's custom/analog and digital implementation and signoff tools; Mentor Graphics' physical verification, design for manufacturing, and circuit verification tools; and Synopsys' ful... » read more

Stacked Die, Phase Two
By Ed Sperling - 09 Apr, 2015 - Comments: 0

The initial hype phase of [getkc id="82" kc_name="2.5D"] appears to be over. There are multiple offerings in development or on the market already from Xilinx, Altera, Cisco, Huawei, IBM, AMD, all focused on better throughput over shorter distances with better yield and lower power. Even Intel has jumped on the bandwagon, saying that 2.5D will be essential for extending [getkc id="74" comment="M... » read more

UPF 3.0 Moves Toward Ratification
By Ann Mutschler - 09 Apr, 2015 - Comments: 0

[gettech id="31044" t_name="UPF"] (Unified Power Format) 3.0 — the fourth incarnation in 10 years — is moving closer to the IEEE ballot process. Erich Marschner, verification architect at [getentity id="22017" e_name="Mentor Graphics"] and vice chair of the [gettech id="31043" comment="IEEE 1801"] working group, explained the working group is as close as possible to being on schedule for... » read more

The Power Estimation Challenge
By Lauro Rizzatti - 09 Apr, 2015 - Comments: 0

If you wonder how important low power is in chip design today, consider the recent news in the blogosphere reporting the controversy surrounding Qualcomm’s Snapdragon 810 SoC — the company’s first flagship 64-bit chip, which will most likely power the top Android devices released in 2015. The story broke in early December along the lines that the 810 had problems with overheating. Whet... » read more

High-Performance Analog And RF Circuit Simulation Using The Analog FastSPICE Platform At Columbia University
By Mentor, a Siemens Business - 08 Apr, 2015 - Comments: 0

The research group led by Professor Peter Kinget at the Columbia University Integrated Systems Laboratory (CISL) focuses on cutting edge analog and RF circuit design using digital nanoscale CMOS processes. Areas of research include design techniques for circuits operating below 1 V, digitally calibrated RF front ends for superior linearity performance, LO synthesizers for wireless applications,... » read more

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