tag: packaging

IC Package Illustrations, From 2D To 3D
By Tyler DeHaan - 21 Jul, 2022 - Comments: 1

In five words or less can you describe what a semiconductor is? Some might say a computer chip, others may say they are "space magic," but I would venture that most people have never heard the word before and would simply say "I have no idea." I was certainly a part of the latter crowd before I began my internship with Amkor Technology where I was brought on board as a 3D illustrator to create ... » read more

Packaging Solutions For Unique Markets
By Marc Mangrum - 16 Jun, 2022 - Comments: 0

The MicroLeadframe (MLF/QFN) packaging technology is the fastest growing IC packaging solution today. From a market segment perspective, MLF packaging solutions represent a >111B-unit market for 2022 across 5 unique markets: automotive, consumer, industrial, computing/networking, and communications. The package solution requirements across these markets varies but, the fundamental values the... » read more

The Race To Zero Defects In Auto ICs
By Anne Meixner - 07 Jun, 2022 - Comments: 0

Assembly houses are fine-tuning their methodologies and processes for automotive ICs, optimizing everything from inspection and metrology to data management in order to prevent escapes and reduce the number of costly returns. Today, assembly defects account for between 12% and 15% of semiconductor customer returns in the automotive chip market. As component counts in vehicles climb from the ... » read more

Challenges For Achieving Automotive Grade 1/0 Reliability In FCBGA and fcCSP Packages
By Knowlton Olmstead - 21 Apr, 2022 - Comments: 0

As the quantity, complexity, and functions of electronic devices in automobiles increase, understanding and characterizing package reliability is of significant concern and importance. The Automotive Electronics Council (AEC) Q-100 specification for Grade 1 and 0 reliability introduces unique challenges as thermal cycling (TC) and high temperature storage (HTS) requirements increase. Additional... » read more

Nip The Defect In The Bud
By Melvin Lee - 12 Apr, 2022 - Comments: 0

As technology nodes shrink, end users are designing systems where each chip element is being targeted for a specific technology and manufacturing node. While designing chip functionality to address specific technology nodes optimizes a chip’s performance regarding that functionality, this performance comes at a cost: additional chips will need to be designed, developed, processed, and assembl... » read more

Finding And Applying Domain Expertise In IC Analytics
By Anne Meixner - 12 Apr, 2022 - Comments: 0

Behind PowerPoint slides depicting the data inputs and outputs of a data analytics platform belies the complexity, effort, and expertise that improve fab yield. With the tsunami of data collected for semiconductor devices, fabs need engineers with domain expertise to effectively manage the data and to correctly learn from the data. Naively analyzing a data set can lead to an uninteresting an... » read more

UCIe: Marketing Ruins It Again
By Brian Bailey - 24 Mar, 2022 - Comments: 1

You may have seen the press release and articles recently about a new standard called UCIe. It stands for Universal Chiplet Interconnect Express. The standard is a great idea and will certainly help the market for chiplet-based designs to advance. But the name — Argggh. More on that later. First, let's talk about what it is. You may notice the name looks similar to PCIe (Peripheral Compone... » read more

Wirebond IC Substrates: Challenges Ahead
By Prasad Dhond - 17 Mar, 2022 - Comments: 0

Substrate suppliers are slashing capacity allocated to wirebond IC substrates. We hear about "limited tenting capacity," "no support for EBS designs," and requests for "conversion to etchback" designs. What does all this mean? Let's start with "Line" and "Space." "Line" is the width of a trace on a substrate and "Space" is the distance between the two traces. For wirebond packages such a... » read more

Addressing The ABF Substrate Shortage With In-Line Monitoring
By Wesley Chou - 08 Mar, 2022 - Comments: 1

Ajinomoto build-up film (ABF) substrate has been a key component in chip manufacturing since its introduction shortly before the turn of the millennium. Substrates made with Ajinomoto build-up film – an electrical insulator designed for complex circuits – are found in PCs, routers, base stations, and servers. Looking ahead, the ABF substrate market will continue to grow, with revenue up ... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part II
By Rahul Singhal - 08 Mar, 2022 - Comments: 0

By Rahul Singhal and Giri Podichetty Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that integrate multiple dies and memories on the same package. Why 2.5D/3D chiplet-based designs for AI SoCs? Many semiconductor companies are adopting chiplet-based d... » read more

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