tag: Synopsys

Strain, Stress In Advanced Packages Drives New Design Approaches
By Ann Mutschler - 19 Dec, 2024 - Comments: 2

Thermal and mechanical stresses are creating significant challenges in heterogeneous chiplet assemblies, increasing the time and cost required to work through all the possible physical effects, dependencies, and interactions, and driving demand for new tools. Unlike in the past, when various components were crammed into a planar SoC on a relatively thick substrate, the new substrates are bei... » read more

Improving Verification Performance
By Brian Bailey - 19 Dec, 2024 - Comments: 0

Without methodology improvements, verification teams would not be able keep up with the growing complexity and breadth of the tasks assigned to them. Tools alone will not provide the answer. The magnitude of the verification task continues to outpace the tools, forcing design teams to seek out better ways to intermix and utilize the tools that are available. But as verification teams take on... » read more

SLM Evolves Into Critical Aspect Of Chip Design And Operation
By Ann Mutschler - 19 Dec, 2024 - Comments: 0

Silicon lifecycle management has evolved greatly in the past five years, moving from novel concept to a key part of design flows at industry leaders such as NVIDIA, Amazon Web Services, Ericsson, and others. Along with becoming a major focus for companies developing semiconductors, the use cases have expanded. While initially focused on post-silicon insights, SLM has expanded to cover the en... » read more

Achieving Successful Multi-Die Signoff
By Vamsi Thatha - 19 Dec, 2024 - Comments: 0

Multi-die designs leveraging 2.5D and 3D technologies are becoming crucial for various electronics applications, including high-performance computing (HPC), artificial intelligence (AI), automotive, and mobile devices. These designs allow the integration of dies from different foundries and technology nodes, enhancing density and interconnect speeds beyond traditional discrete dies. However, th... » read more

Blog Review: Dec. 18
By Jesse Allen - 18 Dec, 2024 - Comments: 0

Siemens’ Michael Munsey predicts that the convergence of AI, advanced packaging, and rise of software-defined products aren’t just incremental changes but will represent a fundamental shift in how we think about semiconductor design and manufacturing. Cadence's Veena Parthan points to hex-core voxels as a significant leap forward for the CFD meshing process that blends the best of struct... » read more

RISC-V Profiles Help Conformance
By Brian Bailey - 18 Dec, 2024 - Comments: 0

Experts At The Table: What's needed to be able to trust that a RISC-V implementation will work as expected across multiple designs using standard OSes. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO of Codasip; Neil Hand, director of marketing at Siemens EDA (at the time of this discussion); Frank Schirrmeist... » read more

TCAD Simulation Challenges For Gate-All-Around Transistors
By Victor Moroz - 17 Dec, 2024 - Comments: 0

By Victor Moroz and Shela Aboud The transition from finFET technology to Gate-All-Around (GAA) technology helps to reduce transistor variability and resume channel length scaling. It also brings several new challenges in terms of transistor design that need to be addressed. One of the challenges is handling the thin Si layers that come with GAA technology, where Si channel thickness scale... » read more

Baby Steps Toward 3D DRAM
By Bryon Moyer - 17 Dec, 2024 - Comments: 0

Flash memory has made incredible capacity strides thanks to monolithic 3D processing enabled by the stacking of more than 200 layers, which is on its way to 1.000 layers in future generations.[1] But the equally important DRAM has achieved a similar manufacturable 3D architecture. The need for a sufficiently large means of storing charge — such as a capacitor — has proved elusive. Severa... » read more

Navigating Increased Complexity In Advanced Packaging
By Gregory Haley - 17 Dec, 2024 - Comments: 1

As chips evolve toward stacked, heterogeneous assemblies and adopt more complex materials, engineers are grappling with new and often less predictable sources of variation. This is redefining what it means to achieve precision, forcing companies to rethink everything from process control and in-line metrology to materials selection and multi-level testing. These assemblies are the result of ... » read more

Chip Industry Week In Review
By The SE Staff - 13 Dec, 2024 - Comments: 0

The 2024 IEEE International Electron Devices Meeting (IEDM) was held this week, prompting a number of announcements from: imec: Proposed a new CFET-based standard cell architecture for the A7 node containing two rows of CFETs with a shared signal routing wall in between, allowing standard cell heights to be reduced from 4 to 3.5T, compared to single-row CFETs. Integrated indium pho... » read more

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