tag: Synopsys

Metrology Advances Step Up To Sub-2nm Device Node Needs
By Laura Peters - 15 Oct, 2024 - Comments: 0

Metrology and inspection are dealing with a slew of issues tied to 3D measurements, buried defects, and higher sensitivity as device features continue to shrink to 2nm and below. This is made even more challenging due to increasing pressure to ramp new processes more quickly. Metrology tool suppliers must exceed current needs by a process node or two to ensure solutions are ready to meet tig... » read more

New Challenges In IC Reliability
By Ed Sperling - 15 Oct, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss reliability of chips, how it is changing, and where the new challenges are, with Steve Pateras, vice president of marketing and business development at Synopsys; Noam Brousard, vice president of solutions engineering at proteanTecs; Harry Foster, chief verification scientist at Siemens EDA; and Jerome Toublanc, high-tech soluti... » read more

Security Concerns Weigh Down Open-Source EDA
By Adam Kovac - 10 Oct, 2024 - Comments: 0

Open-source EDA tools are free, readily available, and growing in numbers, but many chipmakers are wary of using them due to security concerns. On the plus side, proponents say these tools can help attract fresh new talent to chip design. Yet despite their spread online — GitHub alone has more than 140 EDA-specific repositories — using visible source code can provide new avenues of attac... » read more

Managing Legacy In Automotive
By Ann Mutschler - 10 Oct, 2024 - Comments: 0

Experts At The Table: The automotive ecosystem is in the midst of an intense evolution as OEMs and tiered providers grapple with how to deal with legacy technology while incorporating ever-increasing levels of autonomy, electrification, software defined vehicle concepts, just to name a few. Semiconductor Engineering sat down to discuss these and other related issues with Wayne Lyons, senior dir... » read more

The Cost Of EDA Data Storage And Processing Efficiency
By Adam Kovac - 09 Oct, 2024 - Comments: 0

Engineering teams are turning to the cloud to process and store increasing amounts of EDA data, but while the compute resources in hyperscale data centers are virtually unlimited, the move can add costs, slow access to data, and raise new concerns about sustainability. For complex chip designs, the elasticity of the cloud is a huge bonus. With advanced-node chips and packaging, the amount of... » read more

Blog Review: Oct. 9
By Liz Allan - 09 Oct, 2024 - Comments: 0

Siemens’ Stephen Chavez looks at the key benefits and challenges to achieving a successful ECAD-MCAD collaboration. Cadence’s Nayan Gaywala shares the AXI4 locking mechanism when implementing an Xtensa LX-based multi-core system on a Xilinx FPGA platform, using a dual-core design mapped to a KC705 platform as an example. Synopsys’ Vincent van der Leest digs into SRAM PUFs and their ... » read more

Government Chip Funding Spreads Globally
By Liz Allan - 07 Oct, 2024 - Comments: 0

This is the first in a series of articles tracking government chip investments. See part two for Americas-focused funding and part three for the UK and EMEA, and part four for Asia. Countries around the world are ramping up investments into their semiconductor industries as part of new or existing approaches. The increased government activity stems from growing awareness of the strategic imp... » read more

Partitioning In The Chiplet Era
By Ann Mutschler - 03 Oct, 2024 - Comments: 0

The widespread adoption of chiplets in domain-specific applications is creating a partitioning challenge that is much more complex than anything chip design teams have dealt with in previous designs. Nearly all the major systems companies, packaging houses, IDMs, and foundries have focused on chiplets as the best path forward to improve performance and reduce power. Signal paths can be short... » read more

TSMC’s Plan For Closing The Communication Gap
By Barry Pangrle - 03 Oct, 2024 - Comments: 0

TSMC held its North American Open Innovation Platform (OIP) Ecosystem Forum at the Santa Clara County Convention Center on Sept. 25, providing a quick roadmap update and to recognize its partners for all the collaborative work needed to keep the TSMC innovation train rolling and enabling its customers to utilize the latest technologies. L.C. Lu, TSMC fellow and vice president of R&D, sai... » read more

Barriers To Chiplet Sockets
By Brian Bailey - 30 Sep, 2024 - Comments: 0

Experts At The Table: Demand for chiplets is growing, but debate continues about whether standards and general-purpose chiplets will kick-start the commercialization boom, or whether success will come through customization of those chiplets. Semiconductor Engineeering sat down to discuss these and other related issues with Elad Alon, CEO of Blue Cheetah; Mark Kuemerle, vice president of technol... » read more

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