The Chiplet Race Begins


Momentum is building for the development of advanced packages and systems using so-called chiplets, but the technology faces some challenges in the market. A group led by DARPA, as well as Marvell, zGlue and others are pursuing chiplet technology, which is a different way of integrating multiple dies in a package or system. In fact, the Defense Advanced Research Projects Agency (DARPA), part... » read more

Debug Issues Grow At New Nodes


Debugging and testing chips is becoming more time-consuming, more complicated, and significantly more difficult at advanced nodes as well as in advanced packages. The main problem is that there are so many puzzle pieces, and so many different use cases and demands on those pieces, that it's difficult to keep track of all the changes and potential interactions. Some blocks are "on" sometimes,... » read more

Testing Cars In Context


The choices for companies developing systems or components that will work in autonomous vehicles is to road test them for millions of miles or to simulate them, or some combination of both. Simulation is much quicker, and it has worked well in the semiconductor world for decades. Simulating a chip or electronic system in context is hard enough. But simulating a system of systems in the real... » read more

Preparing For A 5G World


Semiconductor Engineering sat down to talk about challenges and progress in 5G with Yorgos Koutsoyannopoulos, president and CEO of Helic; Mike Fitton, senior director of strategic planning and business development at Achronix; Sarah Yost, senior product marketing manager at National Instruments; and Arvind Vel, director of product management at ANSYS. What follows are excerpts of that conversat... » read more

Security Holes In Machine Learning And AI


Machine learning and AI developers are starting to examine the integrity of training data, which in some cases will be used to train millions or even billions of devices. But this is the beginning of what will become a mammoth effort, because today no one is quite sure how that training data can be corrupted, or what to do about it if it is corrupted. Machine learning, deep learning and arti... » read more

Improving Test Coverage And Eliminating Test Escapes Using Analog Defect Analysis


While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of tools to analyze the test coverage during design has made it difficult for designers to address the issue. In this white paper, we explore the methodology for performing analog fault simulation of test coverage based on defect-oriented testing. In addition, we look at h... » read more

Putting “Design” Back Into Design For Test In PCB Products


Design for manufacturing (DFM) has become a proactive part of the design process, but the same cannot be said for DFT. Whereas “left-shifting” DFM has reduced manufacturing problems, increased yield, reduced scrap levels, and simplified engineering rework, testability-related improvements have stayed flat during that same time. Unfortunately, as assembly costs have come down, and test-relat... » read more

Software-Defined Test And Measurement


Software-defined radios, instrumentation and test are ramping up alongside a flood of new technologies related to assisted and autonomous vehicles, 5G, and military/aerospace electronics, breathing new life and significant change into the test and measurement market. Software-defined test adds flexibility in markets where the products and protocols are evolving or still being defined, and wh... » read more

How Automotive ICs Are Reshaping Semiconductor Test


The growth of a new IC market creates ripples along the entire supply chain. Today, we see the semiconductor industry reacting to the needs of the growing automotive IC market, including the development of new IC test tools and methods. The automotive IC market is far and away the fastest growing end-use market with 15% CAGR (according to IC Insights). It is also seeing many new players. Mar... » read more

Tech Talk: Faster Simulation


Cadence’s Adam Sherer talks about how to speed up simulation in complex multi-core designs. https://youtu.be/lDgMwU5KN7U » read more

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