tag: Accellera

Tools And Flows In 2015
By Brian Bailey - 29 Jan, 2015 - Comments: 0

This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already res... » read more

Industry Scorecard For 2014
By Brian Bailey - 22 Dec, 2014 - Comments: 0

At the end of last year, Semiconductor Engineering asked the industry about the developments they expected to see in 2014. If you care to refresh your memory, they were categorized under markets, semiconductors and development tools. Now it is time to look back and see how accurate those predictions were and where they fell short. Part one addressed the market and semiconductor areas and in thi... » read more

The Internet Of Cores
By Brian Bailey - 20 Nov, 2014 - Comments: 0

Ever since the birth of the third-party [getkc id="43" comment="IP"] market, there has been a desire for plug-and-play compatibility between cores. Part of the value proposition of reuse is that a block has been used before, and has been verified and validated by having been implemented in silicon. By re-using the core, many of these tasks no longer land on the [getkc id="81" kc_name="SoC"] dev... » read more

Energy Boost For Power Standards
By Brian Bailey - 09 Oct, 2014 - Comments: 0

If the amount of standards work and industry effort that is being expended on a given topic is any indicator of the growing importance of a design concern, then power has most certainly become the hottest topic in the industry. Thankfully, it seems as if everyone has learned their lessons from the CPF/[gettech id="31044" t_name="UPF"] struggles and is attempting to coordinate activities, while ... » read more

Accellera Updates UVM Standard
By Ed Sperling - 01 Jul, 2014 - Comments: 2

Accellera uncorked its backward-compatible UVM 1.2 standard, which fixes dozens of bugs, including sequences for run-time phasing and support for multithreading. “We’ve solved more than a dozen incompatibilities and improved overall productivity,” said Intel’s Thomas Alsop, who serves as co-chair of the UVM (Universal Verification Methodology) working group. “This is a major releas... » read more

The Week In Review: Design
By Ed Sperling - 06 Jun, 2014 - Comments: 0

Tools Mentor Graphics rolled out embedded Linux software for AMD’s x86 G-series SoCs, code-named Steppe Eagle and its Crowned Eagle CPUs. Ansys-Apache and TowerJazz have created a power noise and reliability signoff design kit, including reference flow guidelines, test case examples and flow setup guidance. Synopsys updated its verification portfolio with static and formal tools for CD... » read more

Executive Insight: Adnan Hamid
By Brian Bailey - 22 May, 2014 - Comments: 1

Semiconductor Engineering sat down with Adnan Hamid, founder and CEO of Breker Verification Systems. Breker was founded in 2003 and has been concentrating on the creation of verification methodologies for multiprocessor SoCs using graph-based entry methods – something that became a hot topic at DVCon 2014 after Mentor Graphics decided to donate its format to Accellera for standardization. ... » read more

The Week In Review: Design
By Ed Sperling - 09 May, 2014 - Comments: 0

Tools Ansys-Apache rolled out a new version of its power noise and reliability tool for finFET-based designs. Given the fact that dynamic power is going to be a massive headache at 14/16nm and beyond due to much greater density, this is a first step in dealing with it. This is just the beginning of a massive effort by EDA to retool for finFETs and the 2.5D/3D architectures. Synopsys rolled... » read more

Blog Review: April 2
By Ed Sperling - 02 Apr, 2014 - Comments: 0

Mentor’s Nazita Saye compares roadway roundabouts to networked systems. One roundabout works fine, but add in a bunch of them and you have a massive traffic jam. How many roundabouts are in your design? Cadence’s Richard Goering interviews Stan Kroliskoski, chair of the IEEE Design Automation Standards Committee, about four working groups on EDA standards and what’s ahead. Speaking ... » read more

Get Ready For DVCon Europe
By Accellera - 28 Mar, 2014 - Comments: 0

By Martin Barnasconi DVCon Europe, a new conference and exhibition around design and verification, will be held Oct. 14-15 in Munich, Germany. Call for abstracts for DVCon Europe is open through April 8. The obvious question is why DVCon Europe. DVCon and its predecessor conferences have been held successfully in the Silicon Valley for more than 20 years. The conference is extremely success... » read more

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