tag: Accellera

The Week In Review: Design
By Ed Sperling - 09 May, 2014 - Comments: 0

Tools Ansys-Apache rolled out a new version of its power noise and reliability tool for finFET-based designs. Given the fact that dynamic power is going to be a massive headache at 14/16nm and beyond due to much greater density, this is a first step in dealing with it. This is just the beginning of a massive effort by EDA to retool for finFETs and the 2.5D/3D architectures. Synopsys rolled... » read more

Blog Review: April 2
By Ed Sperling - 02 Apr, 2014 - Comments: 0

Mentor’s Nazita Saye compares roadway roundabouts to networked systems. One roundabout works fine, but add in a bunch of them and you have a massive traffic jam. How many roundabouts are in your design? Cadence’s Richard Goering interviews Stan Kroliskoski, chair of the IEEE Design Automation Standards Committee, about four working groups on EDA standards and what’s ahead. Speaking ... » read more

Get Ready For DVCon Europe
By Accellera - 28 Mar, 2014 - Comments: 0

By Martin Barnasconi DVCon Europe, a new conference and exhibition around design and verification, will be held Oct. 14-15 in Munich, Germany. Call for abstracts for DVCon Europe is open through April 8. The obvious question is why DVCon Europe. DVCon and its predecessor conferences have been held successfully in the Silicon Valley for more than 20 years. The conference is extremely success... » read more

The Week In Review: Design
By Ed Sperling - 07 Mar, 2014 - Comments: 0

Tools Synopsys rolled out a new version of its software technologies for static and formal verification, which it says increases performance by up to five times. Also new are improved debug and low-power verification with native power simulation, and an integrated IP portfolio. Cadence uncorked a new version of its PCB and packaging environment, which it says speeds up timing closure by as ... » read more

2014 Accellera Standards Are Built on Powerful Shoulders
By Accellera - 27 Jan, 2014 - Comments: 0

By Adam Sherer Looking out at the fresh snow coating the landscape here in Buffalo, it’s tempting to look toward 2014 and focus only on the fresh and new. However, if I’ve learned anything about this city from the day I arrived here as a freshman EE in 1984, it’s that you don’t bury your foundation. Instead, you recognize it as your greatest strength, the powerful shoulders upon whic... » read more

Blog Review: Jan. 8
By Ed Sperling - 08 Jan, 2014 - Comments: 0

How do you choose an embedded operating system—and do you even need one? Mentor’s Colin Walls looks at the options, and the reason why there are no simple answers. Cadence’s Richard Goering has evidence that Facebook is gaining in popularity for engineer. He’s not the first person to recognize this shift, but the big unanswered questions are, ‘What’s the average age of those use... » read more

Where Is 2.5D?
By Ed Sperling - 19 Dec, 2013 - Comments: 3

After nearly five years of concentrated research, development, test chips and characterization, 2.5D remains a possibility for many companies but a reality for very few. So what’s taking so long and why hasn’t all of this hype turned into production runs instead of test chips? Semiconductor Engineering spent the past two months interviewing dozens of people on this subject, from chipmakers ... » read more

Blog Review: Nov. 27
By Ed Sperling - 27 Nov, 2013 - Comments: 0

Synopsys’ Brent Gregory is looking at real-world experiments to figure out which EDA software is better. Make sure to check out his stats. Cadence’s Brian Fuller interviews two Samsung engineers in a video about the image technology in smart phone cameras and just how far it’s progressed. Hint: Don’t forget to charge your phone on your next vacation. Mentor’s Colin Walls points ... » read more

IEEE 1801 UPF Tutorial
By Various Writers - 22 Nov, 2013 - Comments: 0

This tutorial from DVCon 2013 covers the basics of Accellera UPF and then focuses on the features of IEEE 1801 that enable the description of more sophisticated power management systems. The tutorial also provides recommendations regarding migration from Accellera UPF to IEEE 1801 and the methodology changes that are required. And, it presents a UPF-based design flow highlighting the practical ... » read more

Community, Collaboration And Standards
By Yatin Trivedi - 20 Nov, 2013 - Comments: 0

EDA tools/methodologies and semiconductor IP creation are strongly driven by standards. Dating back to the 1980s, standards have helped shape electronic design industry – from the way we design silicon to the way we do business. Indeed, [getentity id="22024" comment="Accellera"] was formed from a merger of two leading standards bodies in the early 1990s, [getentity id="22025" comment="VHDL In... » read more

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