tag: advanced packaging

Bump Co-Planarity And Inconsistencies Cause Yield, Reliability Issues
By Karen Heyman - 11 Oct, 2022 - Comments: 0

Bumps are a key component in many advanced packages, but at nanoscale levels making sure all those bumps have a consistent height is an increasing challenge. Without co-planarity, surfaces may not properly adhere. That can reduce yield if the problem is not identified in packaging, or it can cause reliability problems in the field. Identifying those issues requires a variety of process steps... » read more

Heterogeneous Integration: Exposing Large Panels With Fewer Shots
By John Chang - 11 Oct, 2022 - Comments: 0

By John Chang, with Corey Shay, James Webb, and Timothy Chang The More than Moore era is upon us, as manufacturers increasingly turn to back-end advances to meet the next-generation device performance gains of today and tomorrow. In the advanced packaging space, heterogeneous integration is one tool helping accomplish these gains by combining multiple silicon nodes and designs inside one pac... » read more

Week In Review: Manufacturing, Test
By Karen Heyman and Anne Meixner - 30 Sep, 2022 - Comments: 0

Highlights from ITC The hot topic at this week’s International Test Conference (ITC) was tackling silent data corruption, with panel discussions, papers, and Google’s Parthasarathy Ranganathan’s keynote address all emphasizing the urgency of the issue. In the past two years Meta, Google, and Microsoft have reported on silent errors, errors not detected at test, which are adversely impact... » read more

Improving Redistribution Layers for Fan-out Packages And SiPs
By Laura Peters - 15 Sep, 2022 - Comments: 2

Redistribution layers (RDLs) are used throughout advanced packaging schemes today including fan-out packages, fan-out chip on substrate approaches, fan-out package-on-package, silicon photonics, and 2.5D/3D integrated approaches. The industry is embracing a variety of fan-out packages especially because they deliver design flexibility, very small footprint, and cost-effective electrical connect... » read more

Next Generation Chip Embedding Technology For High Efficiency Power Modules and Power SiPs
By ASE - 15 Sep, 2022 - Comments: 0

Cost, performance, and package size are some of the key drivers required in the next generation of package interconnect and package structure evolution. Embedding active die into substrates was mainly driven by package miniaturization for communication handheld devices. However, in the case of power modules, miniaturization is not the only driver that enhances the need for embedded die substrat... » read more

Designing For Thermal
By Karen Heyman - 13 Sep, 2022 - Comments: 0

Heat has emerged as a major concern for semiconductors in every form factor, from digital watches to data centers, and it is becoming more of a problem at advanced nodes and in advanced packages where that heat is especially difficult to dissipate. Temperatures at the base of finFETs and GAA FETs can differ from those at the top of the transistor structures. They also can vary depending on h... » read more

Making 5G More Reliable
By Ed Sperling - 08 Sep, 2022 - Comments: 0

The rollout of 5G is a complex and monumental effort involving multiple separate systems that need to function flawlessly together in real-time, making it difficult to determine where problems might arise, or how and when to test for them. Investments in 5G have been underway for the better part of a decade, and the technology is considered the next huge growth opportunity for mobile devices... » read more

Enabling Test Strategies For 2.5D, 3D Stacked ICs
By Laura Peters - 08 Sep, 2022 - Comments: 0

Improved testability, coupled with more tests at more insertion points, are emerging as key strategies for creating reliable, heterogeneous 2.5D and 3D designs with sufficient yield.  Many changes need to fall into place to make side-by-side 2.5D and 3D stacking approaches cost-effective, particularly for companies looking to integrate chiplets from different vendors. Today, nearly all of t... » read more

Hybrid Bonding Basics: What Is Hybrid Bonding?
By Jessica Albright - 18 Aug, 2022 - Comments: 2

Hybrid bonding is the key to paving an innovative future in advanced packaging. Hybrid bonding provides a solution that enables higher bandwidth and increased power and signal integrity. As the industry is looking to enhance the performance of final devices through scaling system-level interconnections, hybrid bonding provides the most promising solution with the ability to integrate several di... » read more

Fan-Out Packaging Gets Competitive
By Karen Heyman and Laura Peters - 18 Aug, 2022 - Comments: 0

Fan-out wafer-level packaging (FOWLP) is a key enabler in the industry shift from transistor scaling to system scaling and integration. The design fans out the chip interconnects through a redistribution layer instead of a substrate. Compared to flip-chip ball grid array (FCBGA) or wire bonds, it creates lower thermal resistance, a slimmer package, and potentially lower costs. Yet, if the h... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy