tag: advanced packaging

Next-Gen Design Challenges
By Ed Sperling - 20 Apr, 2021 - Comments: 0

As more heterogeneous chips and different types of circuitry are designed into one system, that all needs to be simulated, verified and validated before tape-out. Aveek Sarkar, vice president of engineering at Synopsys, talks with Semiconductor Engineering about the intersection of scale complexity and systemic complexity, the rising number of corners, and the reduced margin with which to buffe... » read more

Foundry Wars Begin
By Mark LaPedus - 19 Apr, 2021 - Comments: 3

Leading-edge foundry vendors are gearing up for a new, high-stakes spending and technology race, setting the stage for a possible shakeup across the semiconductor manufacturing landscape. In March, Intel re-entered the foundry business, positioning itself against Samsung and TSMC at the leading edge, and against a multitude of foundries working at older nodes. Intel announced plans to build ... » read more

Debug And Traceability Of MCMs And Chiplets In The Manufacturing Test Process
By Guy Cortez - 16 Apr, 2021 - Comments: 0

Single die packages and products have been the norm for decades. Moreover, so has multi-chip modules (MCMs) or system in package (SiP) for quite some time. Understandably, with ASICs and SoCs becoming larger while silicon geometries continue to get smaller, there is an opportunity to combine even more functionality into a smaller form factor for the end product. Hence, new advancements in desig... » read more

Making Chip Packaging More Reliable
By Mark LaPedus - 15 Apr, 2021 - Comments: 0

Packaging houses are readying the next wave of IC packages, but these products must prove to be reliable before they are incorporated into systems. These packages involve several advanced technologies, such as 2.5D/3D, chiplets and fan-out, but vendors also are working on new versions of more mature package types, like wirebond and leadframe technologies. As with previous products, packaging... » read more

3D Stacking For Performance And Efficiency
By Brian Cline - 08 Apr, 2021 - Comments: 0

Moore’s Law scaling is slowing down and limited improvements in performance, power, area, and cost are available from one process node to the next. As a result, advanced packaging and 3D stacking technologies are taking a front seat as the key drivers for next-generation high-performance energy-efficient designs. These types of system-in-package (SiP) technologies require designers to reima... » read more

What Goes Wrong In Advanced Packages
By Ed Sperling - 24 Mar, 2021 - Comments: 1

Advanced packaging may be the best way forward for massive improvements in performance, lower power, and different form factors, but it adds a whole new set of issues that were much better understood when Moore's Law and the ITRS roadmap created a semi-standardized path forward for the chip industry. Different advanced packaging options — system-in-package, fan-outs, 2.5D, 3D-IC — have a... » read more

The Future Of Transistors And IC Architectures
By Mark LaPedus - 18 Mar, 2021 - Comments: 1

Semiconductor Engineering sat down to discuss chip scaling, transistors, new architectures, and packaging with Jerry Chen, head of global business development for manufacturing & industrials at Nvidia; David Fried, vice president of computational products at Lam Research; Mark Shirey, vice president of marketing and applications at KLA; and Aki Fujimura, CEO of D2S. What follows are excerpt... » read more

Hunting For Open Defects In Advanced Packages
By Anne Meixner - 17 Mar, 2021 - Comments: 5

Catching all defects in chip packaging is becoming more difficult, requiring a mix of electrical tests, metrology screening, and various types of inspection. And the more critical the application for these chips, the greater the effort and the cost. Latent open defects continue to be the bane of test, quality, and reliability engineering. Open defects in packages occur at the chip-to-substra... » read more

Designing 2.5D Systems
By Brian Bailey - 15 Mar, 2021 - Comments: 0

As more designs hit the reticle limit, or suffer from decreasing yield, migrating to 2.5D designs may provide a path forward. But this kind of advanced packaging also comes with some additional challenges. How you adapt and change your design team may be determined by where your focus has been in the past, or what you are trying to achieve. There are business, organizational, and technical c... » read more

Tradeoffs To Improve Performance, Lower Power
By Ann Mutschler - 11 Mar, 2021 - Comments: 0

Generic chips are no longer acceptable in competitive markets, and the trend is growing as designs become increasingly heterogeneous and targeted to specific workloads and applications. From the edge to the cloud, including everything from vehicles, smartphones, to commercial and industrial machinery, the trend increasingly is on maximizing performance using the least amount of energy. This ... » read more

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