tag: advanced packaging

The Increasingly Uneven Race To 3nm/2nm
By Mark LaPedus and Ed Sperling - 24 May, 2021 - Comments: 2

Several chipmakers and fabless design houses are racing against each other to develop processes and chips at the next logic nodes in 3nm and 2nm, but putting these technologies into mass production is proving both expensive and difficult. It's also beginning to raise questions about just how quickly those new nodes will be needed and why. Migrating to the next nodes does boost performance an... » read more

Advanced Packaging’s Next Wave
By Mark LaPedus - 20 May, 2021 - Comments: 0

Packaging houses are readying the next wave of advanced packages, enabling new system-level chip designs for a range of applications. These advanced packages involve a range of technologies, such as 2.5D/3D, chiplets, fan-out and system-in-package (SiP). Each of these, in turn, offers an array of options for assembling and integrating complex dies in an advanced package, providing chip custo... » read more

Chiplets: A Solution For The Shortage Of Chips
By Andy Heinig - 13 May, 2021 - Comments: 1

These days, there are new reports on the shortage of chips almost every day. Currently, this issue is affecting mainly car manufacturers such as Audi, Ford, and more. But other system manufacturers, such as in the machine construction industry, are also facing this challenge. Even manufacturers of mass-produced articles such as game consoles are reporting the same problems. The problem is sure ... » read more

In-Chip Sensing And PVT Monitoring: Not Just An Insurance Policy
By Ramsay Allen - 11 May, 2021 - Comments: 0

You wouldn’t drive an expensive car without insurance or take a flight in an aircraft without performing instrument and control surface checks. So why would you take the risk of designing a multi-million dollar advanced node semiconductor device without making sure you are aware of, and able to manage, the dynamic conditions that had the potential to make or break a silicon product? Advanced... » read more

Testing Analog Circuits Becoming More Difficult
By SE Staff - 11 May, 2021 - Comments: 1

Foundries and packaging houses are wrestling how to control heat in the testing phase, particularly as devices continue to shrink and as thermally sensitive analog circuits are added into SoCs and advanced packages to support everything from RF to AI. The overriding problem is that heat can damage chips or devices under test. That's certainly true for digital chips developed at advanced node... » read more

Steep Spike For Chip Complexity And Unknowns
By Ed Sperling - 05 May, 2021 - Comments: 0

Cramming more and different kinds of processors and memories onto a die or into a package is causing the number of unknowns and the complexity of those designs to skyrocket. There are good reasons for combining all of these different devices into an SoC or advanced package. They increase functionality and can offer big improvements in performance and power that are no longer available just b... » read more

Next-Gen Design Challenges
By Ed Sperling - 20 Apr, 2021 - Comments: 0

As more heterogeneous chips and different types of circuitry are designed into one system, that all needs to be simulated, verified and validated before tape-out. Aveek Sarkar, vice president of engineering at Synopsys, talks with Semiconductor Engineering about the intersection of scale complexity and systemic complexity, the rising number of corners, and the reduced margin with which to buffe... » read more

Foundry Wars Begin
By Mark LaPedus - 19 Apr, 2021 - Comments: 3

Leading-edge foundry vendors are gearing up for a new, high-stakes spending and technology race, setting the stage for a possible shakeup across the semiconductor manufacturing landscape. In March, Intel re-entered the foundry business, positioning itself against Samsung and TSMC at the leading edge, and against a multitude of foundries working at older nodes. Intel announced plans to build ... » read more

Debug And Traceability Of MCMs And Chiplets In The Manufacturing Test Process
By Guy Cortez - 16 Apr, 2021 - Comments: 0

Single die packages and products have been the norm for decades. Moreover, so has multi-chip modules (MCMs) or system in package (SiP) for quite some time. Understandably, with ASICs and SoCs becoming larger while silicon geometries continue to get smaller, there is an opportunity to combine even more functionality into a smaller form factor for the end product. Hence, new advancements in desig... » read more

Making Chip Packaging More Reliable
By Mark LaPedus - 15 Apr, 2021 - Comments: 0

Packaging houses are readying the next wave of IC packages, but these products must prove to be reliable before they are incorporated into systems. These packages involve several advanced technologies, such as 2.5D/3D, chiplets and fan-out, but vendors also are working on new versions of more mature package types, like wirebond and leadframe technologies. As with previous products, packaging... » read more

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