tag: advanced packaging

Problems And Solutions In Analog Design
By Ann Mutschler - 05 Aug, 2020 - Comments: 1

Advanced chip design is becoming a great equalizer for analog and digital at each new node. Analog IP has more digital circuitry, and digital designs are more susceptible to kinds of noise and signal disruption that have plagued analog designs for years. This is making the design, test and packaging of SoCs much more complicated. Analog components cause the most chip production test failures... » read more

Memory Access In AI Systems
By Ed Sperling - 27 Jul, 2020 - Comments: 0

Memory access is a key consideration in AI system design. Ron Lowman, strategic marketing manager for IP at Synopsys, talks about how memory affects overall power consumption, why partitioning of on-chip and off-chip is so critical to performance and power, and how this changes from the cloud to the edge. » read more

The Race To Much More Advanced Packaging
By Mark LaPedus - 23 Jul, 2020 - Comments: 2

Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages. Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides mo... » read more

eFPGAs Vs. FPGA Chiplets
By Ed Sperling - 22 Jul, 2020 - Comments: 0

Embedded FPGAs are a totally different concept from discrete FPGA chiplets, and that is reflected in size, cost, power and performance. Geoff Tate, CEO of Flex Logix, talks about which applications are best for each, how each maximizes power and performance, and why choices will vary greatly by application. Related eFPGA Knowledge Center FPGA Knowledge Center Increasing EFPGA Densit... » read more

EDA On Board With New Package Options
By Ann Mutschler - 22 Jul, 2020 - Comments: 2

A groundswell of activity around multi-die integration and advanced packaging is pushing EDA companies to develop integration strategies that speed up time to sign-off, increase confidence that a design will work as expected, while still leaving enough room for highly customized solutions. Challenges range from how to architect a design, how to explore the best options and configurations, ho... » read more

Ins And Outs Of In-Circuit Monitoring
By Ed Sperling - 21 Jul, 2020 - Comments: 2

At 7nm and 5nm, in-circuit monitoring is becoming essential. Steve Crosher, CEO of Moortec, talks about the impact of rising complexity, how different use cases and implementations can affect reliability and uptime, and why measuring electrical, voltage and thermal stress can be used to statistically predict failures and improve reliability throughout a chip’s lifetime. » read more

Next Challenge: Known Good Systems
By Ed Sperling - 07 Jul, 2020 - Comments: 0

The leading edge of design is heading toward multi-die/multi-chiplet architectures, and an increasing number of mainstream designs likely will follow as processing moves closer to the edge. This doesn't mean every chipmaker will be designing leading-edge chips, of course. But more devices will have at least some leading-edge logic or will be connected over some advanced interconnect scheme t... » read more

Advanced Packaging Makes Testing More Complex
By Bryon Moyer - 07 Jul, 2020 - Comments: 1

The limits of monolithic integration, together with advances in chip interconnect and packaging technologies, have spurred the growth of heterogeneous advanced packaging where multiple dies are co-packaged using 2.5D and 3D approaches. But this also raises complex test challenges, which are driving new standards and approaches to advanced-package testing. While many of the showstopper issues... » read more

China Speeds Up Advanced Chip Development
By Mark LaPedus - 22 Jun, 2020 - Comments: 18

China is accelerating its efforts to advance its domestic semiconductor industry, amid ongoing trade tensions with the West, in hopes of becoming more self-sufficient. The country is still behind in IC technology and is nowhere close to being self-reliant, but it is making noticeable progress. Until recently, China’s domestic chipmakers were stuck with mature foundry processes with no pres... » read more

Spreading Out The Cost At 3nm
By Ed Sperling - 18 Jun, 2020 - Comments: 5

The current model for semiconductor scaling doesn't add up. While it's possible that markets will consolidate around a few basic designs, the likelihood is that no single SoC will sell in enough volume to compensate for the increased cost of design, equipment, mask sets and significantly more testing and inspection. In fact, even with slew of derivative chips, it may not be enough to tip the ec... » read more

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