tag: advanced packaging

The Week In Review: Design
By Jesse Allen - 09 Jun, 2017 - Comments: 1

Tools Mentor added new tools to its high-level synthesis portfolio. The DesignChecks tool helps find bugs during coding with a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. The synthesis-aware Coverage tool measures code coverage for C++ signoff and fast closure of synthesized RTL. It sup... » read more

Board Level Reliability Improvement In eWLB
By STATS ChipPAC - 05 Jun, 2017 - Comments: 0

When it comes to reducing form-factor and increasing functional integration of mobile devices, Wafer Level Packaging (WLP) is an attractive packaging solution with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP (FOWLP), it is a more optimal and promising solution compared to fan-in WLP because it can offer greater flexibilit... » read more

Tech Talk: System In Package
By Ed Sperling - 05 Jun, 2017 - Comments: 0

ASE fellow and senior technical advisor William Chen talks about advanced packaging options and why they are now so important. » read more

Implementing High-Density-Advanced Packaging For OSATs And Foundries
By Mentor, a Siemens Business - 05 Jun, 2017 - Comments: 0

HDAP design and verification require cooperation and collaboration between design houses, OSATs, foundries, and EDA vendors. By using common tools that have the integration and functionality needed to operate in both the IC and packaging domains and by developing and deploying process optimized design-kits such as ADK’s and PDKs, OSATs, foundries, and their customers can achieve design, fabri... » read more

Samsung Unveils Scaling, Packaging Roadmaps
By Ed Sperling - 24 May, 2017 - Comments: 5

Samsung Foundry unveiled an aggressive roadmap that scales down to 4nm, and which includes a fan-out wafer-level packaging technology that bridges chips in the redistribution layer, 18nm FD-SOI, and a new organizational structure that allows the unit much greater autonomy as a commercial enterprise. The moves put [getentity id="22865" e_name="Samsung Foundry"] in direct competition with [get... » read more

Reworking Established Nodes
By Ed Sperling - 24 May, 2017 - Comments: 2

New technology markets and a flattening in smartphone growth has sparked a resurgence in older technology processes. For many of these up-and-coming applications, there is no compelling reason to migrate to the latest process node, and equipment companies and fabs are rushing to fill the void. As with all electronic devices, the focus is on cost-cutting. But because these markets are likely ... » read more

Moore’s Law: Toward SW-Defined Hardware
By Ed Sperling - 15 May, 2017 - Comments: 2

Pushing to the next process node will continue to be a primary driver for some chips—CPUs, FPGAs and some ASICS—but for many applications that approach is becoming less relevant as a metric for progress. Behind this change is a transition from using customized software with generic hardware, to a mix of specialized, heterogeneous hardware that can achieve better performance with less ene... » read more

2.5D, Fan-Out Inspection Issues Grow
By Ed Sperling - 12 May, 2017 - Comments: 0

As advanced packaging moves into the mainstream, packaging houses and equipment makers are ratcheting up efforts to solve persistent metrology and inspection issues. The goal is to lower the cost of fan-outs, [getkc id="82" kc_name="2.5D"] and [getkc id="42" kc_name="3D-IC"], along with a number of other packaging variants consistent with the kinds of gains that are normally associated with Moo... » read more

Advanced Packaging Goes Mainstream
By Ed Sperling - 08 May, 2017 - Comments: 0

The roadmap for shrinking digital logic will continue for at least the next 10 years. For others devices, particularly analog, it will slow down or end. And therein lies one of the most fundamental changes in semiconductor design and manufacturing in the past half century. This is no longer just talk. Apple is using a fan-out architecture in its iPhone 7. Memory makers are stacking NAND and ... » read more

Ultra-Thin Substrate Assembly Challenges For Advanced Flip Chip Package
By STATS ChipPAC - 08 May, 2017 - Comments: 0

Advanced semiconductor packaging requirements for higher and faster performance in a thinner and smaller form factor continues to grow for mobile, network and consumer devices. While the increase in device input/output (I/O) count is driven by the famous “Moore’s Law”, the packaging industry is experiencing opposing trends for more complex packaging solutions while the expected cost targe... » read more

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