Advanced Packaging Goes Mainstream

After decades of work, there are now plenty of commercial success stories.

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The roadmap for shrinking digital logic will continue for at least the next 10 years. For others devices, particularly analog, it will slow down or end. And therein lies one of the most fundamental changes in semiconductor design and manufacturing in the past half century.

This is no longer just talk. Apple is using a fan-out architecture in its iPhone 7. Memory makers are stacking NAND and DRAM. Intel has developed a slimmed down embedded bridge for connecting chips. AMD has created graphics chips based on 2.5D. Cisco and Huawei are building networking chips based on silicon interposers. And all of the packaging houses and design services companies are reporting a surge in multi-die packaging business.

After two decades of dabbling in multi-chip architectures, from classic MCMs to fan-outs, 2.5D and even 3D, advanced packaging is quietly going mainstream. And that trend is expected to continue and even expand for several reasons:

• It’s easier to push electrons through wider pipes. There is less concern about resistance and capacitance. And it can be done using bulk CMOS rather than more exotic materials, which are more expensive, harder to source, and more difficult to work with.
• Moving memory or I/O chips next to processors and connecting them with a high-speed interconnect means signals need to travel a shorter distance using those wider pipes than if everything was put on the same chip. As a result, performance increases and the amount of power necessary to drive those signals decreases.
• Tolerances for noise and thermal effects decrease as features shrink. If everything is on the same die there is less distance between devices on a chip. Dynamic power density goes up, and the dielectrics that serve as insulators are thinner. The result is effectively a lower signal-to-noise ratio, which makes designing chips more difficult, particularly if they include sensitive analog components.

Advanced packaging holds the potential to solve many of these problems. The challenge now is incorporating all of this into an ecosystem that has spent the past 52 years focused on shrinking features as a way of both increasing performance—it’s still faster to put the same features on a die than on a board—and lowering the cost, because it takes less area if they all can be put on a single die. Those benefits are no longer easy to obtain just by moving to the next node, though, and leakage current once again becomes problematic at each new node after 16/14nm.

There are two steps that need to be overcome, though, for advanced packaging to live up to its potential. First, more companies need to be more open about working with other companies in the supply chain. To a certain degree this is already underway, and packaging houses, system design companies and foundries all report much more cross-company collaboration than in the past. The supply chain needs to include far more companies, however. The ecosystem cannot afford any finger-pointing if something goes wrong over issues such as mishandling known good die or counterfeit parts slipping into the supply chain.

Second, chipmakers need to begin designing components and extensively characterizing them based upon multiple new criteria to allow more flexibility regarding how these components are packaged together and fewer problems once they are. That means testing for more corner cases on the design side that were never considered when everything was added onto a single die. And it means creating awareness of all of the pieces that potentially can be used in a package so that architects can peruse a menu of possible choices to build the best system for a particular application.

Advanced packaging has long been considered a big opportunity for putting design freedom back into chipmaking. As early as 2001, analog companies were talking about the need to put analog and digital functionality on separate chips. Sixteen years later, the market finally seems to be ready to accept that and more. And given what’s ahead at 5nm and beyond, this shift couldn’t come a moment sooner.

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