Week In Review: Semiconductor Manufacturing, Test

By Gregory Haley - 19 May, 2023 - Comments: 0

TECHCET is forecasting semiconductor precursor revenues, both for high-ƙ metal dielectrics and low-ƙ dielectrics, will increase in the second half of 2023, rebounding from the current zero percent growth rate. Wafer start volumes are expected to rebound in 2024 with expansions in 2nm and 3nm logic devices. SEMI also predicts the global slump in semiconductor sales will end this quarter, gi... » read more

Metrology Strategies For 2nm Processes

By Laura Peters - 07 Mar, 2023 - Comments: 3

Metrology and wafer inspection processes are changing to keep up with evolving and new device applications. While fab floors still have plenty of OCD tools, ellipsometers, and CD-SEMs, new systems are taking on the increasingly 3D nature of structures and the new materials they incorporate. For instance, processes like hybrid bonding, 3D NAND flash devices, and nanosheet FETs are pushing the bo... » read more

Measuring 3D Sidewall Topography & LER for Photoresist Patterns Using Tip-Tilting AFM Technology

By Technical Paper Link - 19 Feb, 2023 - Comments: 0

A new technical paper titled "Enhancing the precision of 3D sidewall measurements of photoresist using atomic force microscopy with a tip-tilting technique" by researchers at National Metrology Institute of Japan (NMIJ) and National Institute of Advanced Industrial Science and Technology (AIST). "We have developed a technique for measuring the sidewall of the resist pattern using atomic for... » read more

Unknowns And Challenges In Advanced Packaging

By Ed Sperling - 19 Jan, 2023 - Comments: 0

Dick Otte, CEO of Promex Industries, sat down with Semiconductor Engineering to talk about unknowns in material properties, the impact on bonding, and why environmental factors are so important in complex heterogeneous packages. What follows are excerpts of that conversation. SE: Companies have been designing heterogeneous chips to take advantage of specific applications or use cases, but th... » read more

Metrology Options Increase As Device Needs Shift

By Laura Peters - 10 Jan, 2023 - Comments: 1

Semiconductor fabs are taking an ‘all hands on deck’ approach to solving tough metrology and yield management challenges, combining tools, processes, and other technologies as the chip industry transitions to nanosheet transistors on the front end and heterogenous integration on the back end. Optical and e-beam tools are being extended, while X-ray inspection is being added on a case-by-... » read more

Research Bits: Dec. 13

By Jesse Allen - 13 Dec, 2022 - Comments: 0

Electronic-photonic interface for data centers Engineers at Caltech and the University of Southampton integrated an electronic and photonic chip for high-speed communication in data centers. "There are more than 2,700 data centers in the U.S. and more than 8,000 worldwide, with towers of servers stacked on top of each other to manage the load of thousands of terabytes of data going in and o... » read more

Metrology Of Thin Resist For High NA EUVL

By Nova - 16 Nov, 2022 - Comments: 0

One of the many constrains of high numerical aperture extreme ultraviolet lithography (High NA EUVL) is related to resist thickness. In fact, one of the consequences of moving from current 0.33NA to 0.55NA (high NA) is the depth of focus (DOF) reduction. In addition, as the resist feature lines shrink down to 8nm half pitch, it is essential to limit the aspect ratio to avoid pattern collapse. T... » read more

Deep Learning To Classify And Establish Structure Property Predictions With PeakForce QNM Atomic Force Microscopy

By Bruker - 07 Sep, 2022 - Comments: 0

Machine learning and specifically, deep learning, is a powerful tool to establish the presence (or absence) of microstructure correlations to bulk properties with its ability to flesh out relationships and trends that are difficult to establish otherwise. This application note discusses the use of deep learning tools, to explore AFM phase and PeakForce Quantitative Nanomechanics (QNM) im... » read more

Particle Removal From EUV Photomasks

By Technical Paper Link - 31 Aug, 2022 - Comments: 0

This technical paper titled "AFM-Based Hamaker Constant Determination with Blind Tip Reconstruction" was just published by researchers at ASML, RWTH Aachen University, and AMO GmbH. The research reports a vaccuum AFM-based approach for particle removal from EUV photomasks. Find the technical paper here. Published August 2022. Ku, B., van de Wetering, F., Bolten, J., Stel, B., van de K... » read more

Nanosheet FETs Drive Changes In Metrology And Inspection

By Karen Heyman - 09 Aug, 2022 - Comments: 0

In the Moore’s Law world, it has become a truism that smaller nodes lead to larger problems. As fabs turn to nanosheet transistors, it is becoming increasingly challenging to detect line-edge roughness and other defects due to the depths and opacities of these and other multi-layered structures. As a result, metrology is taking even more of a hybrid approach, with some well-known tools moving... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?