CEO Outlook: More Data, More Integration, Same Deadlines

By Ed Sperling - 24 Jun, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What ... » read more

Bumps Vs. Hybrid Bonding For Advanced Packaging

By Mark LaPedus - 23 Jun, 2021 - Comments: 3

Advanced packaging continues to gain steam, but now customers must decide whether to design their next high-end packages using existing interconnect schemes or move to a next-generation, higher-density technology called copper hybrid bonding. The decision is far from simple, and in some cases both technologies may be used. Each technology adds new capabilities in next-generation advanced pac... » read more

An Advanced Infrastructure To Enable Secure, Cloud-Aware Design And Processed Data EDA Tool Interoperability

By Si2 - 22 Jun, 2021 - Comments: 0

By Rajeev Jain, Kerim Kalafala, and Ramond Rodriguez Significant technology disruptions are on the horizon that will provide massive efficiency gains for EDA tool suppliers and semiconductor companies alike. These disruptions include the application of artificial intelligence and machine learning to enhance supplier tools and optimize user design flows and methodologies, and the ensuing migr... » read more

Shifting Toward Data-Driven Chip Architectures

By Ed Sperling and Ann Mutschler - 16 Jun, 2021 - Comments: 0

An explosion in data is forcing chipmakers to rethink where to process data, which are the best types of processors and memories for different types of data, and how to structure, partition and prioritize the movement of raw and processed data. New chips from systems companies such as Google, Facebook, Alibaba, and IBM all incorporate this approach. So do those developed by vendors like Appl... » read more

Power/Performance Bits: June 15

By Jesse Allen - 15 Jun, 2021 - Comments: 0

Low-loss photonic IC Researchers at EPFL built a photonic integrated circuit with ultra-low loss. The team focused on silicon nitride (Si3N4), which has orders of magnitude lower optical loss compared to silicon. It is used in low-loss applications such as narrow-linewidth lasers, photonic delay lines, and nonlinear photonics. In applying the material to photonic ICs, they took advantage... » read more

Changes In Sensors And DSPs

By Ed Sperling - 14 Jun, 2021 - Comments: 0

Pulin Desai, group director for product marketing, management and business development at Cadence, talks about why processing is moving closer to the end point, how to save energy through reduced area and sensor fusion, and the impact of specialization, 3D capture and always-on circuits. » read more

Thermal Floorplanning For Chips

By Brian Bailey - 10 Jun, 2021 - Comments: 0

Heat management is becoming crucial to an increasing number of chips, and it's one of a growing number of interconnected factors that must be considered throughout the entire development flow. At the same time, design requirements are exacerbating thermal problems. Those designs either have to increase margins or become more intelligent about the way heat is generated, distributed, and dissi... » read more

Accelerating AI/ML Inferencing With GDDR6 DRAM

By Frank Ferro - 10 Jun, 2021 - Comments: 0

The origins of graphics double data rate (GDDR) memory can be traced to the rise of 3D gaming on PCs and consoles. The first graphics processing units (GPU) packed single data rate (SDR) and double data rate (DDR) DRAM – the same solution used for CPU main memory. As gaming evolved, the demand for higher frame rates at ever higher resolutions drove the need for a graphics-workload specific me... » read more

Customizing Chips For Power And Performance

By Ed Sperling - 10 Jun, 2021 - Comments: 0

Sandro Cerato, senior vice president and CTO of the Power & Sensor Systems Business Unit at Infineon Technologies, sat down with Semiconductor Engineering to talk about fundamental shifts in chip design with the rollout of the edge, AI, and more customized solutions. What follows are excerpts of that conversation. SE: The chip market is starting to fall into three distinct buckets, the e... » read more

Accelerate Adoption Of High-Speed, Low-Latency, Cache-Coherent Standards Using Formal Verification

By Cadence - 09 Jun, 2021 - Comments: 0

We continue to see huge growth in data and compute demand, fueled by increased global data traffic with the 5G rollout, the prevalence of streaming services, and expanded artificial intelligence and machine learning (AI/ML) applications. Several new industry-standard specifications have emerged in recent years to define the protocols of the underlying electronic components and IP building block... » read more

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Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.