tag: ALD

Research Bits: June 13
By Jesse Allen - 13 Jun, 2023 - Comments: 0

Converting heat to electricity Researchers at the National Institute of Standards and Technology (NIST) and University of Colorado Boulder fabricated a device to boost the conversion of heat into electricity. The technique involves depositing hundreds of thousands of microscopic columns of gallium nitride atop a silicon wafer. Layers of silicon are then removed from the underside of the waf... » read more

ALD-Oxide Semiconductors: Summary, Benefits And Challenges
By Technical Paper Link - 31 May, 2023 - Comments: 0

A technical paper titled "Atomic layer deposition for nanoscale oxide semiconductor thin film transistors: review and outlook" was published by researchers at Hanyang University. "In this review, to introduce ALD-oxide semiconductors, we provide: (a) a brief summary of the history and importance of ALD-based oxide semiconductors in industry, (b) a discussion of the benefits of ALD for oxide... » read more

Surface-Activated ALD For Room-Temperature Bonding of Al2O3
By Technical Paper Link - 03 Apr, 2023 - Comments: 0

A new technical paper titled "Room-temperature bonding of Al2O3 thin films deposited using atomic layer deposition" was published by researchers at Kyushu University. Abstract "In this study, room-temperature wafer bonding of Al2O3 thin films on Si thermal oxide wafers, which were deposited using atomic layer deposition (ALD), was realized using the surface-activated bonding (SAB) metho... » read more

Large Area Process For Atomically Thin 2D Semiconductor, Using Scalable ALD
By Technical Paper Link - 30 Mar, 2023 - Comments: 0

A new technical paper titled "Large-area synthesis of high electrical performance MoS2  by a commercially scalable atomic layer deposition process" by researchers at the University of Southampton, LMU Munich, and VTT Technical Research Centre of Finland. Abstract: "This work demonstrates a large area process for atomically thin 2D semiconductors to unlock the technological upscale required... » read more

2D Semiconductor Materials Creep Toward Manufacturing
By Katherine Derbyshire - 16 Feb, 2023 - Comments: 0

As transistors scale down, they need thinner channels to achieve adequate channel control. In silicon, though, surface roughness scattering degrades mobility, limiting the ultimate channel thickness to about 3nm. Two-dimensional transition metal dichalcogenides (TMDs), such as MoS2 and WSe2, are attractive in part because they avoid this limitation. With no out-of-plane dangling bonds and at... » read more

How Far Will Copper Interconnects Scale?
By Laura Peters - 15 Dec, 2022 - Comments: 0

As leading chipmakers continue to scale finFETs — and soon nanosheet transistors — to ever-tighter pitches, the smallest metal lines eventually will become untenable using copper with its liner and barrier metals. What comes next, and when, is still to be determined. There are multiple options being explored, each with its own set of tradeoffs. Ever since IBM introduced the industry to c... » read more

High-Temperature Stable Spin-On Carbon Materials For Advanced Pattern Transfer Applications
By Brewer Science - 16 Jun, 2022 - Comments: 0

In recent years a strong demand has arisen for spin-on carbon (SOC) materials compatible with high-temperature processes. This requirement is to enable usage of high-temperature SOC (HTSOC) materials in integration schemes utilizing chemical vapor deposition (CVD) and/or atomic layer deposition (ALD) processes. In addition to compatibility with the high-temperature deposition processes, planari... » read more

Highly Selective Etch Rolls Out For Next-Gen Chips
By Mark LaPedus - 21 Mar, 2022 - Comments: 0

Several etch vendors are starting to ship next-generation selective etch tools, paving the way for new memory and logic devices. Applied Materials was the first vendor to ship a next-gen selective etch system, sometimes called highly-selective etch, in 2016. Now, Lam Research, TEL, and others are shipping tools with highly-selective etch capabilities, in preparation for futuristic devices su... » read more

Extending Copper Interconnects To 2nm
By Laura Peters - 17 Mar, 2022 - Comments: 0

Transistor scaling is reaching a tipping point at 3nm, where nanosheet FETs will likely replace finFETs to meet performance, power, area, and cost (PPAC) goals. A significant architectural change is similarly being evaluated for copper interconnects at 2nm, a move that would reconfigure the way power is delivered to transistors. This approach relies on so-called buried power rails (BPRs) and... » read more

Using Process Modeling To Enhance Device Uniformity During Self-Aligned Quadruple Patterning
By Timothy Yang - 18 Nov, 2021 - Comments: 0

Despite the growing interest in EUV lithography, self-aligned quadruple patterning (SAQP) still holds many technical advantages in pattern consistency, simplicity, and cost. This is particularly true for very simple and periodic patterns, such as line & space patterns or hole arrays. The biggest challenge of SAQP is the inherently asymmetric mask shape. This asymmetry can create structural ... » read more

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