tag: ALD

The Thermal Trap: How Dielectrics Limit Device Performance
By Gregory Haley - 20 Nov, 2025 - Comments: 1

The spread of artificial intelligence is forcing an uncomfortable truth on semiconductor manufacturing. Thin films, which are essential for isolating signals and insulating different components and metal layers, are becoming heat traps as physical dimensions continue to shrink in chips used inside AI data centers. That, in turn, is limiting how fast these chips can process data and increasing t... » read more

Precision Under Pressure: Managing Materials Complexity In Advanced Packaging
By Gregory Haley - 18 Sep, 2025 - Comments: 0

In the race to extend Moore's Law through advanced packaging, the limits of precision are no longer defined solely by lithography. Increasingly, they are dictated by the unpredictable behavior of materials. Semiconductor packaging today is no longer limited to just silicon and copper. It includes an expanding range of polymers, adhesives, dielectrics, exotic metals, along with substrates suc... » read more

The End Of Copper Interconnects?
By Katherine Derbyshire - 21 Aug, 2025 - Comments: 0

After nearly three decades, the era of copper interconnects may be coming to an end. Sort of. At interconnect CDs below 10nm, copper is no longer the best metallization choice. Yet it remains unsurpassed for larger features. The most serious challenge to continued copper scaling is the metal’s dramatic increase in resistivity at dimensions below its relatively large (40nm) mean free path l... » read more

Dielectrics for 2D TMDs, Including Deposition Strategies And Emerging Dielectric Materials (Cambridge)
By Technical Paper Link - 08 Jul, 2025 - Comments: 0

A new technical paper titled "Gate dielectrics for transistors based on two-dimensional transition metal dichalcogenide semiconductors" was published by researchers at University of Cambridge. "This perspective analyses the state of the art on 2D TMD and dielectric interfaces, highlighting key challenges in depositing oxide dielectrics on top of atomically thin TMD semiconductors. We provide... » read more

Viability of aZnMIm As A Resist For EUV Lithography (Johns Hopkins, Northwestern, Intel et al.)
By Technical Paper Link - 27 Jun, 2025 - Comments: 0

A new technical paper (preprint) titled "Extreme Ultraviolet and Beyond Extreme Ultraviolet Lithography using Amorphous Zeolitic Imidazolate Resists Deposited by Atomic/Molecular Layer Deposition" was published by researchers at Johns Hopkins University, Northwestern University, Intel Corporation, Bruker Nano, EUV Tech and Lawrence Berkeley National Lab. The paper states "This study demonstr... » read more

Challenges Grow For Medical ICs
By Gregory Haley - 03 Mar, 2025 - Comments: 0

Demand for medical ICs used inside and outside the body is growing rapidly, but unique manufacturing and functional requirements coupled with low volumes have turned this into a complex and extremely challenging market. Few semiconductor applications demand this level of precision, reliability, and long-term stability. Unlike consumer electronics, where failure might mean a reboot or chip re... » read more

Demonstration Of An ALD IWO Channel In A GAA Nanosheet FET Structure (Georgia Tech, Micron)
By Technical Paper Link - 14 Feb, 2025 - Comments: 0

A new technical paper titled "First Demonstration of High-Performance and Extremely Stable W-Doped In2O3  Gate-All-Around (GAA) Nanosheet FET" was published by researchers at Georgia Institute of Technology and Micron. Abstract "We demonstrate a gate-all-around (GAA) nanosheet FET featuring an atomic layer-deposited (ALD) tungsten (W)-doped indium oxide (In2O3), or indium tungsten oxide ... » read more

What’s Next For Through-Silicon Vias
By Laura Peters - 06 Jan, 2025 - Comments: 0

From large TSVs for MEMS to nanoTSVs for backside power delivery, cost-effective process flows for these interconnects are essential for making 2.5D and 3D packages more feasible. Through-silicon vias (TSVs) enable shorter interconnect lengths, which reduces chip power consumption and latency to carry signals faster from one device to another or within a device. Advanced packaging technology... » read more

Navigating Increased Complexity In Advanced Packaging
By Gregory Haley - 17 Dec, 2024 - Comments: 1

As chips evolve toward stacked, heterogeneous assemblies and adopt more complex materials, engineers are grappling with new and often less predictable sources of variation. This is redefining what it means to achieve precision, forcing companies to rethink everything from process control and in-line metrology to materials selection and multi-level testing. These assemblies are the result of ... » read more

Monolithic Vs. Heterogeneous Integration
By Ed Sperling - 24 Oct, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss two very different paths forward for semiconductors and what's needed for each, with Jamie Schaeffer, vice president of product management at GlobalFoundries; Dechao Guo, director of advanced logic technology R&D at IBM; Dave Thompson, vice president at Intel; Mustafa Badaroglu, principal engineer at Qualcomm; and Thomas Po... » read more

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