tag: Aldec

Week In Review: Design, Low Power
By Jesse Allen - 01 Apr, 2022 - Comments: 0

Tools Synopsys introduced a new model for using its EDA tools on the cloud. Synopsys Cloud provides pay-as-you-go access to the company's cloud-optimized design and verification products, with pre-optimized infrastructure on Microsoft Azure to address higher levels of interdependencies in chip development. "As more design flows incorporate AI, requiring even more resources, the virtually unlim... » read more

Designing Chips In A ‘Lawless’ Industry
By Ed Sperling - 02 Aug, 2021 - Comments: 2

The guideposts for designing chips are disappearing or becoming less relevant. While engineers today have many more options for customizing a design, they have little direction about what works best for specific applications or what the return on investment will be for those efforts. For chip architects, this is proving to be an embarrassment of riches. However, that design freedom comes wit... » read more

Developing A Real-Time SDR System
By Mariusz Grabowski - 29 Jul, 2021 - Comments: 0

As telecommunication technologies evolve there is an on-going drive for the development of high-performance systems for radio communications. Part of that evolution involves implementing components in software functions that had traditionally been implemented in hardware. Software-defined radio (SDR) is a prime example. Significant amounts of signal processing have been handed over to the ge... » read more

Automated Conversion Of Xilinx Vivado Projects To ALINT-PRO
By Aldec - 28 Jul, 2021 - Comments: 0

Aldec's ALINT-PRO design verification solution performs static RTL and design constraints code analysis to uncover critical design issues early in the design cycle. The product helps FPGA developers rise to the challenge of designing large FPGA designs and multiprocessor system on chip devices that include high-capacity and high-performance FPGA hardware. The solution supports running rule c... » read more

Week In Review: Design, Low Power
By Jesse Allen - 23 Jul, 2021 - Comments: 0

Tools Cadence unveiled Cerebrus Intelligent Chip Explorer, a new machine learning-based tool to drive the Cadence RTL-to-signoff implementation flow. The tool aims to use reinforcement learning to find flow solutions that otherwise might not be explored and applies models to future designs. The company says it can improve productivity up to 10X and PPA up to 20% with optimization of the flow f... » read more

Week In Review: Design, Low Power
By Jesse Allen - 09 Jul, 2021 - Comments: 0

Tools Aldec extended its TySOM family of embedded prototyping boards with the introduction of TySOM-M-MPFS250, the first in a planned series to feature a Microchip PolarFire SoC FPGA MPFS250T-FCG1152 and to have dual FMC connectivity. The board contains 16Gb FPGA DDR4 x32, 16Gb MSS DDR4 x36 with ECC, eMMC, SPI Flash memory, 64 Kb EEPROM and a microSD card socket. The PolarFire SoC is a five-st... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 09 Jul, 2021 - Comments: 0

Pervasive computing — IoT, edge, cloud, data center, and back The IoT designer Deed designed a screenless health monitor, worn on the wrist, that uses IoT (Internet of Things) building blocks from Infineon Technologies. The Get bracelet interprets hand gestures for making payments, picking up phone calls, turning up or down audio, while it also takes health data and biometrics. The system us... » read more

Blog Review: June 30
By Jesse Allen - 30 Jun, 2021 - Comments: 0

Siemens EDA's Chris Spear considers what classes should represent in SystemVerilog and offers two major categories along with some helpful UVM tips. Cadence's Paul McLellan listens in on keynotes at the recent TSMC Technology Symposium, including TSMC CEO C. C. Wei's introduction some of the fab's new offerings, such as an automotive-focused N5 process. Synopsys' Dennis Kengo Oka notes th... » read more

Rocky Road To Designing Chips In The Cloud
By Ann Mutschler - 24 Jun, 2021 - Comments: 0

EDA is moving to the cloud in fits and starts as tool vendors sort out complex financial models and tradeoffs while recognizing a potentially big new opportunity to provide unlimited processing capacity using a pay-as-you-go approach. By all accounts, a tremendous amount of tire-kicking is happening now as EDA vendors and users delve into the how and why of moving to the cloud for chip desig... » read more

Power, Performance — Avionics Designers Want It All
By Heidi Elliott - 10 Jun, 2021 - Comments: 0

Not long ago, the prevailing philosophy among chip designers for aviation systems could be summed up as, “I feel the need — the need for speed.” Today, aviation’s top guns have pulled back on the throttle a bit. There’s a more nuanced discussion balancing the need for performance versus power, with other factors coming into consideration such as safety, security certifications and ove... » read more

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