tag: Aldec

Giant Auto Industry Disruption Ahead
By Ed Sperling - 29 Jan, 2018 - Comments: 5

The move to self-driving vehicles over the next decade or so will result in a massive restructuring of entire segments of the global economy that have evolved to create and support automobiles and the people who drive them. The shift will create many new jobs-particularly for semiconductors and electronic systems-and conservatively it will eliminate hundreds of thousands of existing ones. It... » read more

Analyzing Data Differently
By Sunil Sahoo - 25 Jan, 2018 - Comments: 0

Data analysis is often a very time consuming process for a hardware design or verification engineer. We always end up using the waveform viewer which may not be very efficient in giving us a high-level overview of what we’re looking for. Data that is spread across a long simulation cycle is very hard to visualize on the waveform. Whenever I have to analyze a huge chunk of data, I always wonde... » read more

The Week In Review: Design
By Jesse Allen - 19 Jan, 2018 - Comments: 0

M&A Barco Silex, now named Silex Inside, split from parent company Barco in a management buyout in partnership with a group of private investors lead by Dutch investment company Vehold BV. The company will continue its focus on security, video compression, and interface IP, along with design services. Tools & IP Mentor is making a version of its HyperLynx design rule checking tool ... » read more

Partitioning With Ease
By Henry Chan - 21 Dec, 2017 - Comments: 0

Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more FPGAs are required. The capacity and pin limitations of FPGAs create constraints for how the ASIC/SoC design can be mapped into the FPGAs. Aldec’s HES-DVM's prototyping mode accou... » read more

The Week In Review: Design
By Jesse Allen - 15 Dec, 2017 - Comments: 0

M&A Synopsys finalized its acquisition of Black Duck Software, which provides software for managing and securing open source software in projects, adding to Synopsys' burgeoning software analysis and security business. The cash deal was approximately $547 million net of cash acquired. STMicroelectronics acquired Atollic, maker of the Eclipse-based TrueSTUDIO Integrated Development Envir... » read more

Big Challenges, Changes For Debug
By Ann Mutschler - 04 Dec, 2017 - Comments: 1

By Ann Steffora Mutschler & Ed Sperling Debugging a chip always has been difficult, but the problem is getting worse at 7nm and 5nm. The number of corner cases is exploding as complexity rises, and some bugs are not even on anyone's radar until well after devices are already in use by end customers. An estimated 39% of verification engineering time is spent on debugging activities the... » read more

Using FPGAs For Emulation
By Krzysztof Szczur - 30 Nov, 2017 - Comments: 0

For many years, emulators were available only to verification teams working on the largest projects in companies with deep enough pockets. Due to size rather than capabilities they were called “Big Box” emulators and typically were used in order to recover some of the time lost on RTL simulation. Meanwhile, FPGA technology has been available long enough to mature to the point where FPGA bas... » read more

Prototyping Partitioning Problems
By Ann Mutschler - 30 Nov, 2017 - Comments: 0

Gaps are widening in the prototyping of large, complex chips because the speed and capacity of the FPGA is not keeping pace with rapid rollout pace of advanced ASICs. This is a new twist for a well-established market. Indeed, prototyping with FPGAs is as old as the [gettech id="31071" t_name="FPGAs"] themselves. Even before they were called FPGAs, logic accelerators or LCAs (logic cell ar... » read more

The Week In Review: Design
By Jesse Allen - 17 Nov, 2017 - Comments: 0

Tools Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include improved performance when using code containing many inline randomized calls and up to 29% faster simulation speed of UVM. Pulsic added new features to its Unity Bus Planner for planning... » read more

The Week In Review: Design
By Jesse Allen - 27 Oct, 2017 - Comments: 0

M&A PLDA is divesting its Reflex CES brand. The FPGA board maker will become wholly managed by its own management and investment teams. In 2015, Reflex CES took over the hardware businesses of PLDA, including FPGA-based boards and the System-on-Module product lines. Tools Mentor uncorked a new tool for in-system test and diagnosis of automotive ICs. Tessent MissionMode provides infrast... » read more

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